Switched clamping diodes & input I/V curves with hysteresis

Hello all,

Yesterday, I discussed IBIS with one of our standard logic suppliers.
They provide good Spice support, but are only beginning to get
interested in behavioural models.

Two issues were raised, summarized here for your information:

1) One family of components has a static input I/V characteristics
   which show a hysteresis effect: the response for a 0->1 transition
   is not the same as for a 1->0 transition, due to the design of
   a bus-hold circuit.

   My view is that IBIS doesn't allow this effect to be modelled.

2) One family of components switches out the power clamp
   diode whenever the output buffer is in tri-state.

   My view is that IBIS can model this buffer if the clamping diode
   characteristics are put in the [Pullup] table and the high-impedance
   characteristics in the [POWER Clamp] table.

   However, is there is a potential risk because the simulator
   will assume that the high-impedance characteristic is
   constantly present, which is not the case? The risk is serious
   only if the high-impedance state is not so high (not the
   case for the logic family under discussion)

(There were some concerns also re internal feedback structures,
but the actual problems were not very clear to me.)

Any comments?

John

-- 
John Fitzpatrick   <John.Fitzpatrick@ln.cit.alcatel.fr>    
Alcatel CIT, 4 rue de Broglie, 22304 Lannion, France
Tel: (+33)96.04.79.33  Fax: (+33)96.04.85.09