Hello all,
Thanks to everyone who replied to my question.
It looks like I'm slowly getting to understand the spec!
The general view is that b) is indeed wrong.
Example b) is an LVT18504 model that Sri Jandhyala (TI) sent me a few
months ago when I was interested in seeing how bus-hold can
be modelled.
Example a) is from the CMOS_I/O buffer of Pentium(R)_Pro_Processor,
pentpro.ibs, revision 2.1.
I was interested by Arpad's remark that the "a) example might not
be 100% correct, since it shows the same number for dt
in the typical and minimum places." As the pentpro has
rising and falling waveforms, I guess I should really use them
instead of relying on [Ramp].
Thanks again for your help.
John
ps
Is it possible to search the mail archive? I may have other
such questions that were surely answered long before I got
to know about IBIS
---------------------------------------------------------
Hello all,
A short question regarding interpretation of a model:
In the IBIS 2.1 spec, the ramp rate is defined as
dV 20% to 80% voltage swing
-- = --------------------------------------
dt Time to take to swing the above voltage
When I scan through a random set of IBIS models, I see the
following entries after the [Ramp] keyword of the following
types:
a) dV/dt_r 1.84/0.65n 1.77/0.65n 1.87/0.53n
b) dV/dt_r 4.1/1n 1.6/1n 8.2/1n
>From my point of view, a) is correct, but b) is not good.
I would like to be able to extract dV and dt individually.
As [Ramp] is an obligatory keyword, I hoped it would be
safe to do so .... until I saw b).
Thanks for your help,
John
-- John Fitzpatrick <John.Fitzpatrick@ln.cit.alcatel.fr> Alcatel CIT, 4 rue de Broglie, 22304 Lannion, France Tel: (+33)96.04.79.33 Fax: (+33)96.04.85.09Received on Wed May 15 10:01:51 1996
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