Re: Avoiding Double Counting

Hi,

Thanks to all who had responded to my question on Double counting issues.
Let me ask one more on this topic(see below):

> ** Arpad Writes: **
> Consider an I-V curve for a device driving low (the same is also true for high
> state, but I am not going to address that here). If you sweep it from -Vcc to
> 2*Vcc, you get basically three regions in the I-V curve. First you are
> measuring the GND clamps, which are in the range of -Vcc to 0 V. Then the
> pulldown transistor, between 0 V to Vcc, and above Vcc the power clamp. In
> CMOS, the GND clamp usually comes from the parasitic diode in the pulldown FET,
> but the power clamp comes from the parasitic diode of the pullup transistor.
>
> Now, if you modulate the GND or Vcc voltage in a simulation due to SSO noise,
> the knee voltages of these clamps should also move around with respect to their
> corresponding supply voltages. If you had a single I-V curve, this would not be
> possible. This was the real reason I choose to separate them the way they are
> done now.
>

There are three regions on a Pullup or Pulldown V/I curve:

        -Vcc to 0V 0V to +Vcc +Vcc to +2Vcc

        Gnd Clamp Pu or Pd Power Clamp

So, since GND Clamp and Power Clamp data are provided seperately for a Tri-statable output
(by disabling that outputs), I think the Pu and Pd data could have been taken
only from 0V to +Vcc(during enable mode).

This does not sweep clamp structures, so no substraction of data is necessary, no double
counting issues and the simulator can combine clamp data with 'On' data as
necessary.

When a CMOS device is 'ON', who would want to sweep that above Vcc ...

Regards,
Syed
National Semiconductor Corp.

  
Received on Mon Nov 25 14:32:52 1996