Re[2]: Avoiding Double Counting

Text item:

Syed,

First, D. C. Sessions spoke (wrote) out of my heart.

Second, the reason that the whole sweep range and subtraction is necessary is,
because when the transistor is on, it does add more current to the clamps. In
other words, when you sweep above Vcc while driving low, you get saturation
current plus Vcc clamp current, therefore your clamp current is actually shifted
up by the amount of the saturation current. If you measured the Vcc clamp the
way you described it, it would start from around 0 mA (and not the saturation
current).

Similarly, when you sweep below GND, you get (approximately) the on-channel
resistance current plus GND clamp current...

I don't know of any other way to separate/combine them.

Arpad
================================================================================

Syed Huq wrote:

> Thanks to all who had responded to my question on Double counting issues.
> Let me ask one more on this topic(see below):
>
> > ** Arpad Writes: **
> > Consider an I-V curve for a device driving low (the same is also
true for high
> > state, but I am not going to address that here). If you sweep
it from -Vcc to
> > 2*Vcc, you get basically three regions in the I-V curve. First you are
> > measuring the GND clamps, which are in the range of -Vcc to 0 V. Then the
> > pulldown transistor, between 0 V to Vcc, and above Vcc the power clamp. In
> > CMOS, the GND clamp usually comes from the parasitic diode in
the pulldown FET,
> > but the power clamp comes from the parasitic diode of the pullup
transistor.
> >
> > Now, if you modulate the GND or Vcc voltage in a simulation due
to SSO noise,
> > the knee voltages of these clamps should also move around with
respect to their
> > corresponding supply voltages. If you had a single I-V curve,
this would not be
> > possible. This was the real reason I choose to separate them
the way they are
> > done now.

> There are three regions on a Pullup or Pulldown V/I curve:
>
> -Vcc to 0V 0V to +Vcc +Vcc to +2Vcc
>
> Gnd Clamp Pu or Pd Power Clamp
>
> So, since GND Clamp and Power Clamp data are provided seperately
for a Tri-statable output
> (by disabling that outputs), I think the Pu and Pd data could have been taken
> only from 0V to +Vcc(during enable mode).
>
> This does not sweep clamp structures, so no substraction of data
is necessary, no double
> counting issues and the simulator can combine clamp data with 'On' data as
> necessary.
>
> When a CMOS device is 'ON', who would want to sweep that above Vcc ...

We do -- all the time. After all, when a reflection comes back into
an active output the additional snubbing effect of an ON transistor
makes a huge difference. Especially between the rail and the turnon
point of the clamp structure, where the active device is highly
conductive and the clamp nonexistent. The difference in line settling
time and ringback level is remarkable.

--
D. C. Sessions
dc.sessions@tempe.vlsi.com
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Subject: Re: Avoiding Double Counting
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