R_Pad?

Hello IBIS folk,

I'm participating in my companies initial developement stages of
generating IBIS files, and currently we are simultaniously
investigating generating them from both actual silicon, as well
as from spice netlists. Were new to this email list, so
please excuse us if this has been discussed:

I have searched all of the documents that I could find, including
searching through the email archives, but we are still having
trouble answering this one question: How do we deal with a
Pad resistance (CMOS)... R_comp would have been perfect for this. It
seems that those who asked about R_comp in the past were told
to figure it into the R_package (or R_pin). However, when the data
is collected from real silicon without the package (using a tester's
probe leads directly on the die's I/O pads), any resistance between the
I/O pad and the I/O buffer circuitry gets included... So
the test yeilds Pull-up and Pull-down data that includes an effective
R_comp. For those who have designs with a built-in resistance between
your pad and your I/O circuitry, how did you deal with this since the
specs don't allow for R_comp, and including this resistance in the
R_package is (seems) impossible?

The thing that flagged us to this problem was that our Pull-down curve
(after subtracting the Power-clamp diode data from the initial pull-down
data) gets brought down to close to 0 current when there's about a diode
voltage above Vcc on the pin (in our initial SPICE testing where we
included a resistance between the I/O circuitry and the Pad).

Thanks in advance,
-Scott Schlachter
 Actel Corporation
 Sunnyvale, CA
Received on Tue Oct 22 20:40:04 1996