Re: R_Pad?

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Scott,

I agree with Stephen Peters, that the pad resistance is included in the I-V
curves of the pullup and/or pulldown structures.

This is similar to the resistive properties of the diodes. A pure diode I-V
curve is exponential, and if you plot that equation, you will see currents in
the Giga and Tera Ampere magnitude already at 1 Volt of forward bias. The diode
equation in text books refers to junction voltage, not terminal voltage, and
there is a significant series resistance between the junction and the terminals.

I have seen many SPICE models that ignore the resistive properties of the ESD
diodes, yielding such large currents at 1 Volt of over or undershoot. So much
for the accuracy of the SPICE models...

Real diodes do not have such I-V curves, they usually start out exponentially,
but then straighten out when the resistive properties begin to limit the
current. So, between 1 and 5 volts of forward bias (if the device lets this)
you would get a more or less linear I-V curve with a few Ohms slope. Just like
we don't separate this resistance, I don't think we need to separate the pad
resistance. It just simply modifies the shape of the transistor I-V curves.

Also, in most cases the effect of the pad resistance is so small that I don't
think it would be noticable by just eyeballing the curve (in contrary to the
diode example above). From your EMAIL, it seems to me that you might have a
different problem, if the pad resistance seemed to make such a big difference,
or if the subtraction made an almost 0 pulldown curve. I would be glad to help
you with that problem, but you would have to supply more information. (Your
IBIS model might have beed incorrectly done also).

I hope this helps,

Arpad Muranyi
Intel Corporation
================================================================================

Hello Scott, and fellow IBISains:

    If I recall past conversations correctly, resistance
between the pad and the active xsistors has been accounted
for by including it's effects in the pullup and pullown curves.
At least, that is how I have done models before. I'm
curious however -- do you see a reason why this resistance
should be called out seperatly? It's a good question....

                    Regards,
                    Stephen Peters
                    Intel Corp.

Hello IBIS folk,

I'm participating in my companies initial developement stages of
generating IBIS files, and currently we are simultaniously
investigating generating them from both actual silicon, as well
as from spice netlists. Were new to this email list, so
please excuse us if this has been discussed:

I have searched all of the documents that I could find, including
searching through the email archives, but we are still having
trouble answering this one question: How do we deal with a
Pad resistance (CMOS)... R_comp would have been perfect for this. It
seems that those who asked about R_comp in the past were told
to figure it into the R_package (or R_pin). However, when the data
is collected from real silicon without the package (using a tester's
probe leads directly on the die's I/O pads), any resistance between the
I/O pad and the I/O buffer circuitry gets included... So
the test yeilds Pull-up and Pull-down data that includes an effective
R_comp. For those who have designs with a built-in resistance between
your pad and your I/O circuitry, how did you deal with this since the
specs don't allow for R_comp, and including this resistance in the
R_package is (seems) impossible?

The thing that flagged us to this problem was that our Pull-down curve
(after subtracting the Power-clamp diode data from the initial pull-down
data) gets brought down to close to 0 current when there's about a diode
voltage above Vcc on the pin (in our initial SPICE testing where we
included a resistance between the I/O circuitry and the Pad).

Thanks in advance,
-Scott Schlachter
 Actel Corporation
 Sunnyvale, CA

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From: Stephen Peters <speters@ichips.intel.com>
Date: Wed, 23 Oct 1996 09:43:04 -0700
Subject: R_Pad?
To: ibis@vhdl.org, ibis-users@vhdl.org
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