Re[2]: R_Pad?

Text item:

Scott,

There is no need to take out the parasitic diodes from the MOSFETs in order to
model them correctly (i.e. to include their resistiveness). You are right, that
the current equation itself does not include the resistance, but there is no
need for it. (If you included the resistance in the diode equation, you would
end up with a transcendental equation which is a tough one to work with).

If you have access to an HSPICE manual, look up the RD, RDC, RS, RSC, etc.
parameters. Don't let yourself get confused that these are Drain and Source
resistance numbers; the currents of parasitic diodes go through Drain, Source,
and Bulk. Notice that these resistances all default to zero. This means that
if someone doesn't specify them explicitly, there will be no resistive
parasitics in the model. (Which happens way to often, unfortunately).

Arpad
===============================================================================

Dileep and Arpad:

HSPICE will model the inherent CMOS diodes (D to Bulk) within the transistor
model. From what I can tell, there seems to be a fallback to this
specification
of the model: the diode saturation current equations do not appear to have
any way to include any parasitic resistance whatsoever. I believe
that you both
have valid points here. HSPICE can model the diode correctly, but it seems
that the only way is to extract it from the said transistors, and model it
seperately - a definate unexpected extra step. When modeled this way, there
is no problem assigning the appropriate parasitic impedances associated with
the diodes. However, in trying to keep the power and ground clamp diodes as
being inherently modeled within the pull-up and pull-down transistors, there
seems to be a flaw with the HSPICE model. Perhaps there is something that I'm
overlooking with this, and if anyone knows how to deal with this in the
HSPICE transistor models, please respond. Thanks,
-Scott Schlachter
 Actel Corporation

> Arpad Muranyi, Intel Corporation wrote:
>
> > I have seen many SPICE models that ignore the resistive properties
of the ESD
> > diodes, yielding such large currents at 1 Volt of over or undershoot.
 So much
> > for the accuracy of the SPICE models...
> >
>
> Please do not get confused between the model EQUATIONS and model PARAMETERS.
> SPICE diode model equations have the provision for specifying the parasitic
> resistance. Of course, if it is not specified in the model PARAMETERS,
> it can produce large currents. IBIS models will exhibit similar unrealistic
> behavior if the parasitic resistance is not taken into account while
> making the ibis model from simulations. It is always possible to use a very
> good model improperly to produce unrealistic results. SPICE is not to be
> blamed for that.
>
> ------------------------------------------------------------
> Dileep Divekar
> Applied Simulation Technology, Inc.
> 2188 Bering Drive
> San Jose, CA 95131
>
> Phone - (408)-434-0967 x 100
> Fax - (408)-434-1003
> Email - dileep@apsimtech.com
> ------------------------------------------------------------
>

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Cc: dileep@contec.Apsimtech.COM
Subject: Re: R_Pad?
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From: scotts@actel.com (Scott Schlachter)
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