Re: s2ibis and spice netlist file

IBISfans,

I think I have solved my problem. I noticed that the s2ibis generated
.spi files did not attach the .INCLUDE process_file_names I had
specified in my header files. As such, the process parameters were not
seen by hspice.

The solution would be to go into each and every .spi file and manually
add the .INCLUDE statement with the process_file_name, run hspice,
extract out the V/I data and manually create the .ibs file from all these.

Anyone seen this same problem with s2ibis ?

Regards,
Syed.
National Semiconductor Corp.

> From huq Thu Sep 5 17:29:37 1996
> Date: Thu, 5 Sep 96 17:29:06 PDT
> From: huq (Syed Huq)
> To: ibis-users@vhdl.org
> Subject: s2ibis and spice netlist file
> Cc: huq
> Content-Type> : > X-sun-attachment>
> Content-Length: 31643
>
> Hi,
>
> I am trying to model an input called BTI(See plot.ps attached).
> In my spice netlist file, I have sub-ckt calls like below:
>
> XI1 BTI 0 N0 0 G3 SUB5
> XI0 BTI OUT 0 G3 SUB6
>
> It seems that since these sub-ckt calls mention output
> node(N0 & OUT), I run into various errors saying certain
> pmos nmos not present. G3 is Power.
>
> I do have all pmos nmos models in my process files
>
> Is this a wrong way of modeling an input ? Do I need to remove
> ALL reference to output nodes when modeling an Input ?
>
> Regards,
> Syed.
> National Semiconductor Corp.
Received on Fri Sep 6 14:34:25 1996