RE: standard loads on 66 MHz PCI

The purpose of the test loads is to have a well defined load into which the
semiconductor wendor can test their Tco (Tval) numbers. So when we simulate

flight times, we start our flight time measurements from the point on the
reference waveform where the Tco (Tval) number was measured to. If we
didn't do
it that way, we would have a gap or overlap in our AC spreadhseets and our
timings would be hosed... (Remember, the actual driver has a totally
different
waveform from the reference load waveform, so we can't use that as the
beginning
of the flight time). Greg Edlund is absolutely correct, that for this
reason it
is very important to match the reference load in the simulation to the load
the
manuafturer used to obtain the Tco (Tval) numbers.

Therefore I wold trun around Greg Edlund's question and ask: Do the
semiconductor vendors really use these different reference loads to obtain
their
min and max Tco (Tval) numbers for their chips? In my opinion, these loads
were
not invented for the sake of PCI or the SIE engineer, they were invented for
the
IC manufacturer so that they can provide more meaningful Tco (Tval)
numbers(?).
I only question whether it is really necessary to have different min/max
loads.
The test load (and waveform) doesn't match the driver's real load (and
waveform)
anyway, so why bother making a separate test load for "minimum" and
"maximum"
conditions?

Arpad
============================================================================
==

I wonder if this is really a non-issue? Does the somewhat "unusual" passage
in
the PCI spec about Tval loading necessarily mean that the vendor datasheet
for
that component must use the same loads? Couldn't the vendor specify a
"traditional" standard load in the datasheet and still comply with PCI?

The real concern here is that the load used by the simulator to compute net
delays be IDENTICAL to the one specified in the datasheet. Now, if
component
datasheets are really using the three new PCI loads, then we truly have a
problem. Beside the Motorola SRAM example, does anyone know of any PCI
components that actually use all three loads in the datasheet?

How new are these Tval loads? Version 2.2 (currently in draft, dated June
1998)?

Greg Edlund
Advisory Engineer, AS/400 System Timing
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
11/09/98
04:44 PM ---------------------------

d-haedge@ti.com on 11/09/98 10:20:22 AM
Please respond to d-haedge@ti.com
To: ibis-users@vhdl.org
cc:
Subject: Re: standard loads on 66 MHz PCI

We had a similar problem with a Motorola MPC750. The L2 cache MAX timing
numbers are specified to a 20pF load and the MIN numbers to a 5pF load.
We were using ICX to analyze timing. We looked at the output under no load,

then at 20pF and 5pF. The delta was measured to be 477ps. We then adjusted

the timing sheets in ICX so that the minimum allowed routing distance was
effectively increased by 477ps to compensate for the additional 'test' load.

This allowed us to use a single IBIS model with Cref set at 20pF. You may
be able to apply a similar 'trick' with the PCI driver and Vref.

David Haedge
Raytheon Systems Company
Received on Mon Nov 9 15:56:50 1998