Scaling IBIS models

I have a v2.1 model from a supplier. The models is of
a CMOS 24ma driver. After simulations, I find that the
driver is too strong, that is, there is ringing on the
transitions, and the transition is faster than is
necessary. So I request the supplier to reduce the drive
strength by 10%, rebuild the IBIS models and send me the
new stuff.

I get the new models. I find that the V/I tables show
about a 10% reduction. That is what I expected. But,
the transition times and rising and falling waveforms
are not slower, but faster than the original (by about
10%). I think about this. Perhaps its because the
capacitance of the the gate is reduced. No, the C_comp
value is not changed.

Note: these models are created from a home-grown s2ibis
procedure. These are not measured values.

So the questions: Why does a model with reduced drive
capacity have faster edge rates? Is this a model error
or should it really be so?

Second, if you need to do some "what-if'ing", and you decide
to edit the ibis model to scale it, what things should be
changed and in what direction (that is increased or decreased)?
Should everything scale by the same factor?

 -- Paul Gregory
Received on Wed Nov 11 07:33:01 1998