convergence problem

I am trying to do IBIS modeling of my output buffer (vdd= 3,3.3,3.6 volt). While simulating,
using hspice for getting pull-up data, circuit does't converge for DC as well as TRAN analsis (beyond
3.8volt and below -2volt of out voltage).

And it looks correct that output buffers should not converge (if there are no clamp/ESD diodes) in those
conditions. If that happens that what should I should. Should I truncate the pull-up range (-vdd to vdd*2)
to -2v to 3.8v only. Or there is some other solution possible.

Please help me out. I am stuck.

Thanks in advance,
Sagheer at Interra.
Received on Mon Nov 16 15:35:58 1998