The timing test load parameters

Hello All:

   At last Fridays meeting I was asked to provide a write-up on the
Vmeas, Rref, Cref and Vref parameters. Here it is. This text will
also appear in the next edition of the cookbook.

    Regards,
    Stephen Peters
    Intel Corp.

--------
1. What are Vmeas, Rref, Cref and Vref?

Vmeas, Rref, Cref and Vref represent the output loading conditions under
which a devices Tco (propagation delay or clock-to-output timing) is specified.
These parameters are sometimes referred to as the 'timing test load', and are
documented in a devices data sheet. Please note that the timing test load does
not necessarily represent the load the device sees in a real application.
It is simply the output load the manufacture uses when characterizing a devices
performance.

                         Vref
                         ------
                           |
                           \
                           / Rref
      +-------+ \
      | | |
 -----| DUT |------------+
      | | |
      +-------+ ----
                          ---- Cref
                           |
                          gnd

As shown above, Vref represents a pullup voltage, Rref represents
a load resistance connected to Vref, and Cref is a load capacitance
to ground.

Vmeas is the point on the output waveform at which a Tco measurement is
referenced to. As an example, if Tco (clock to output) for a particular
device is 5ns, this means there is a 5ns delay from when input clock waveform
crosses a specific voltage level to when the output responds by crossing
'Vmeas' volts. See the diagram below.

               +--- Tco ----+
               | |
               | ___________|_____________
               |/ |
    Input + |
      ________/ |
                            |
                            | ______________________
                            |/
   Output ---+------- Vmeas
      _____________________/

2. So why are these parameters included in an IBIS file?

The timing test load parameters are included in an IBIS file to aid the
user (or simulator) in doing system level timing analysis. Given that a
device has a specified propagation delay into the timing test load, the user
can simulate the device as it drives this load and determine how long it takes
the output to switch from quiescence to crossing 'Vmeas' volts. The user can
then do a second simulation with the device driving the actual load, and by
noting the difference in time it takes to cross 'Vmeas' the user can
determine the difference in device propagation delay due to output loading.
This is a major factor when doing system level timing analysis.
Received on Wed Apr 21 09:20:28 1999