s2ibis2 error? in rising/falling waveform generation

All:
I have noticed that s2ibis2 attaches the load resistor (Rload) between
the output
node and vdd(typ) for min and max as well as typ rising/falling waveform
simulations.
I'm guessing that the value for this vdd should track vdd(typ), vdd(min)
and vdd(max)
respectively. If this assumption is true, then be warned - if not,
please let me know so
I can relax and quit bothering you all with this.
--Rob

--
Rob Goodrich
Circuit Design - Advanced Imaging Technology (AIT)
Motorola SPS, I&E Solutions
6501 William Cannon Drive West MD: OE37
Austin, TX 78735
ra3862@email.sps.mot.com
(512) 895-7341