Re: BIRD #61 -- Characterization of Receivers

>>
A NEGATIVE delay is possible for ANY logic circuit. Example: a simple inverter,
with its threshold at any level except exactly Vcc/2. Apply a slow ramp, and
measure the 50% to 50% delay. It will be negative for either the rising or
falling edge (depending on whether the threshold was under/over Vcc/2).
This happens because logic gates switch when they reach a voltage threshold
determined by transistor sizing.

While I would not expect a negative delay for most I/O, it is certainly not
forbidden at light loading. And a negative increment in delay is almost certain
at light loading, as pointed out by others.

Lynne Green
HyperLynx

>> *********
>> * 3 *
>> *********
>>
>> 3) Some delays are negative. This is very very bad.
>> Should be always positive. Just from stand point of
>> causality. You apply a signal and then 1ns BEFORE that event
>> your receiver tells you the signal has arrived.
>> Simulators have to add some 'base' delay.
>> Simulator_A will add 1ns, Simulator_B will add 10ns, etc.
>> Why not IBIS spec add this 'base' delay and all have
>> less headahe?
>>
>
> >>> As I pointed out above, the intent is to show the change in
> propagation delay, and a negative change is perfectly OK.
> Now, you do raise a good issue about 'base delay'. I do not know
> if base delay is an important variable in constructing a
> behavioral receiver model, of if different simulators will come
> up with different models because they assumed different base
> delays. I do assume base delay can be approximated by looking
> at the setup time specification for a particular pin. I hesitate,
> however, to have IBIS spec a 'base delay' -- at least not without
> a lot of simulator vendor input.
>>

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E-Mail: Lynne Green <green@wolfenet.com>
Date: 15-Aug-99
Time: 14:46:38

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Received on Sun Aug 15 15:07:02 1999