Series MOSFET modeling questions...

IBIS Experts,

I have created a template (enclosed) showing what I believe to be the proper
way to model a series MOSFET switch IC (yes, it passes the 3.2 parser!).
However, before I start using the template to create real models, I would
like to settle a few questions:

1) Is the selection of the Vds level for the IV table arbitrary? Or is this
Vds level connected in some way to the pass voltage of the switch at Vcc?

2) It seems to me that the only way to model the enable pins of a switch --
the pins connected to the gates of the FET switches through internal logic
-- is either as "NC" or Terminator pins. Is this correct? Or is there some
other way to model the enable pins so that their function is preserved?

3) The latest parser did not flag errors when I created a model which had
the same sets of pin number pairs assigned to more than one control group
under the [Series Pin Mapping] keyword. Is this intentional?

Thanks in advance!

- Michael Mirmak, Intel Corp.
  FM6-45
  1900 Prairie City Rd.
  Folsom, CA 95630
  (916) 356-4261
  (916) 377-1046 (FAX)
  michael.mirmak@intel.com

 <<s_switch.ibs>>