My thoughts:
The level of the stimulus should (at least for CMOS) be 0 to VCC and
vary with VCC.
If the VT models are going to be accurate, then you should be simulating
enough of the output driver that the edge rate should be a secondary
effect (ie. if you are close to the internal edge rate of the part then
the output answer should not be affected).
This is all assuming that you are generating the VT curves from a SPICE
or other analog simulation.
SHRIPAD RAJ wrote:
> IBIS gurus,
>
> While generating min and max V-T tables in an IBIS model, is it
> necessary to change the level and edge rate of the stimulus?
>
> Thanks
>
> Shripad
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Received on Thu Mar 11 09:05:31 1999
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