Re: How to model a bidirectional trisate device with the input grounded.

Hello,

You could try the following syntax:
(Partial .s2i file)
| Spice_node signal model_name R_pin L_pin C_pin
|-------------------------------------------------------
[Pin]
1 0 GND GND
2 PAD MY_IO Trisate
-> IN ENBL
IN I input dummy1
ENBL OEN enable dummy2
3 VDD PWR POWER
|
|------------------------------------------------------
|

[model] Tristate
[model type] I/O
[Polarity] Non-Inverting
[Enable] active-low
[model file] mymodel.typ mymodel.min mymodel.max
[Rising waveform] 50 0 NA NA NA NA NA NA NA
[Falling waveform] 50 3.3 NA NA NA NA NA NA NA
[Rising waveform] 50 3.3 NA NA NA NA NA NA NA
[Falling waveform] 50 0.0 NA NA NA NA NA NA NA

[model] dummy1
[nomodel]

[model] dummy2
[nomodel]

The mymodel.typ,min,max refers to your process corner models.

You should also refer to the /doc section of s2ibis2 for detailed description
of s2i syntax.

Also look under the /examples dir and see ex2 and ex3 for Tri-state buffer
modeling.

Regards,
Syed.
Cisco Systems, Inc

> X-SMAP-Received-From: outside
> From: laplan@tellabs.com
> Subject: Re: How to model a bidirectional trisate device with the input
grounded.
> To: laplan@tellabs.com (Sandra Laplanche)
> Date: Tue, 16 Mar 1999 10:39:35 -0600 (CST)
> Cc: ibis-users@eda.org, laplan@tellabs.com
> MIME-Version: 1.0
> Content-Transfer-Encoding: 7bit
>
> > Hi,
> >
> > Is anyone looking into my question which is described below?
> >
> >
> > Thanks!
> >
> > Sandra
>
>
>
>
>
>
>
>
> >
> > This is a multi-part message in MIME format.
> >
> > --------------404E71479D4
> > Content-Type: text/plain; charset=us-ascii
> > Content-Transfer-Encoding: 7bit
> >
> > To whom it may concern:
> >
> > My question is how to create an .s2i file for a bidirectional tristate
> > device connected like this. The input (IN) is connected to GND within
> > the chip, the CIN is directed into the chip and is not accessible to me.
> > The OUT is the output pin and it is the only one that is accessible to
> > me. The OEN line is the output enable which is also internal to the chip
> > hence not accessible and it is active low. Hence, the OEN is the only
> > signal that can cause a transition at the output pin. I need also need
> > the .s2i file to generate an rising and falling curve. I have attached
> > the hspice file.
> >
> >
> >
> >
> > /|
> > CIN____/ |____
> > \ | |
> > \| |
> > |
> > |\ |
> > IN ____| \_____|_____ OUT
> > | | /
> > ---- |/o
> > -- |
> > |
> > |
> > OEN
> >
> >
> >
> > Pleae reply to laplan@tellabs.com
> >
> > --------------404E71479D4
> > Content-Type: text/plain; charset=us-ascii; name="fsel.sp"
> > Content-Transfer-Encoding: 7bit
> > Content-Disposition: inline; filename="fsel.sp"
> >
> > * Subcircuit pc3b05 PAD I OEN CIN
> > *.SUBCKT pc3b05 PAD I OEN CIN
> >
> > .LIB '/home/tellabf/vlsitool/vlsi_tech_libraries/hspice_vcmn4/vcmn4.lib' TY
> > .INCLUDE '/home/tellabf/vlsitool/vlsi_tech_libraries/hspice_vcmn4/vcmn4.inc'
> >
> > M1 U15_U12_U6_drain U15_oenb VDD VDD P L=.40U
> > + W=12.00U
> > M2 U15_oenb OEN VDD VDD P L=.40U W=12.00U
> > M3 U15_U12_U6_drain U15_oenb VSS VSS N L=.40U W=9.60U
> > M4 U15_U12_U7_drain U15_oenb U15_U12_U6_drain VSS N L=.40U
> > + W=9.60U
> > M5 U15_bulkdriver VDD U15_U12_U7_drain VSS N L=.40U
> > + W=9.60U
> > M6 U15_bulkdriver U15_U12_U6_drain U15_U12_U10_sour VSS N
> > + L=.40U W=9.60U
> > M7 U15_U12_U10_sour U26_padinv U15_oenb VSS N L=.40U
> > + W=9.60U
> > M8 U15_oenb OEN VSS VSS N L=.40U W=9.60U
> > M9 U15_n_gate I VSS VSS N L=.40U W=19.20U
> > M10 U15_p_gate U15_oenb U15_n_gate VSS N L=.40U W=19.20U
> > M11 U15_p_gate I VDD VDD P L=.40U W=24.00U
> > M12 U15_n_gate OEN U15_p_gate VDD P L=.40U W=24.00U
> > M13 U15_n_gate OEN VSS VSS N L=.40U W=9.60U
> > M14 U15_p_gate U15_oenb VDD VDD P L=.40U W=12.00U
> > M15 U18_pad5vtol VDD PAD VSS N L=1.00U W=49.95U
> > M16 U18_floatbulk U15_bulkdriver VDD U18_floatbulk P L=.50U
> > + W=40.00U
> > M17 U15_bulkdriver VDD PAD U18_floatbulk P L=.50U
> > + W=10.00U
> > M18 U16_pfb VDD PAD U18_floatbulk P L=.50U W=10.00U
> > M19 U17_nbw VSS VSS VSS N L=.40U W=48.00U
> > M20 U17_nfb U18_pad5vtol U17_nbw VSS N L=.40U W=48.00U
> > M21 U17_nfb VSS VDD VDD P L=.40U W=6.00U
> > M22 U26_padinv U18_pad5vtol VDD VDD P L=.40U W=24.00U
> > M23 U18_pad5vtol U26_padinv VDD VDD P L=.50U W=.90U
> > M24 CIN U26_padinv VDD VDD P L=.40U W=36.00U
> > M25 U26_padinv U18_pad5vtol VSS VSS N L=.40U W=9.60U
> > M26 CIN U26_padinv VSS VSS N L=.40U W=19.20U
> > M27 U16_pfb PAD U16_M72$5_source U18_floatbulk P L=.50U
> > + W=10.00U
> > M28 U16_pfb PAD U16_M72$4_source U18_floatbulk P L=.50U
> > + W=10.00U
> > M29 U16_pfb PAD U16_M72$3_source U18_floatbulk P L=.50U
> > + W=10.00U
> > M30 U16_pfb PAD U16_M72$2_source U18_floatbulk P L=.50U
> > + W=10.00U
> > M31 U16_pfb PAD U16_M72$1_source U18_floatbulk P L=.50U
> > + W=10.00U
> > M32 U16_pfb PAD U16_M72$0_source U18_floatbulk P L=.50U
> > + W=10.00U
> > M33 U16_M72$5_source VDD VDD U18_floatbulk P L=.50U
> > + W=10.00U
> > M34 U16_M72$4_source VDD VDD U18_floatbulk P L=.50U
> > + W=10.00U
> > M35 U16_M72$3_source VDD VDD U18_floatbulk P L=.50U
> > + W=10.00U
> > M36 U16_M72$2_source VDD VDD U18_floatbulk P L=.50U
> > + W=10.00U
> > M37 U16_M72$1_source VDD VDD U18_floatbulk P L=.50U
> > + W=10.00U
> > M38 U16_M72$0_source VDD VDD U18_floatbulk P L=.50U
> > + W=10.00U
> > M39 U16_U1_drain U15_oenb VSS VSS N L=.40U W=9.60U
> > M40 U16_pfb VDD U16_U1_drain VSS N L=.40U W=9.60U
> > M41 PAD U17_nfb U19_M62$5_source VSS N L=.50U W=54.00U
> > M42 PAD U17_nfb U19_M62$4_source VSS N L=.50U W=54.00U
> > M43 PAD U17_nfb U19_M62$3_source VSS N L=.50U W=54.00U
> > M44 PAD U17_nfb U19_M62$2_source VSS N L=.50U W=54.00U
> > M45 PAD U17_nfb U19_M62$1_source VSS N L=.50U W=54.00U
> > M46 PAD U17_nfb U19_M62$0_source VSS N L=.50U W=54.00U
> > M47 U19_M62$5_source U15_n_gate VSS VSS N L=.50U
> > + W=54.00U
> > M48 U19_M62$4_source U15_n_gate VSS VSS N L=.50U
> > + W=54.00U
> > M49 U19_M62$3_source U15_n_gate VSS VSS N L=.50U
> > + W=54.00U
> > M50 U19_M62$2_source U15_n_gate VSS VSS N L=.50U
> > + W=54.00U
> > M51 U19_M62$1_source U15_n_gate VSS VSS N L=.50U
> > + W=54.00U
> > M52 U19_M62$0_source U15_n_gate VSS VSS N L=.50U
> > + W=54.00U
> > M53 U21_M61$11_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M54 U21_M61$10_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M55 U21_M61$9_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M56 U21_M61$8_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M57 U21_M61$7_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M58 U21_M61$6_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M59 U21_M61$5_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M60 U21_M61$4_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M61 U21_M61$3_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M62 U21_M61$2_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M63 U21_M61$1_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M64 U21_M61$0_drain U15_p_gate VDD U18_floatbulk P L=.50U
> > + W=66.80U
> > M65 PAD U16_pfb U21_M61$11_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M66 PAD U16_pfb U21_M61$10_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M67 PAD U16_pfb U21_M61$9_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M68 PAD U16_pfb U21_M61$8_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M69 PAD U16_pfb U21_M61$7_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M70 PAD U16_pfb U21_M61$6_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M71 PAD U16_pfb U21_M61$5_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M72 PAD U16_pfb U21_M61$4_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M73 PAD U16_pfb U21_M61$3_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M74 PAD U16_pfb U21_M61$2_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M75 PAD U16_pfb U21_M61$1_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M76 PAD U16_pfb U21_M61$0_drain U18_floatbulk P L=.50U
> > + W=66.80U
> > M79 U25_MNUN3$1_drai U25_R1_r1 VSS VSS N L=.50U
> > + W=54.00U
> > M80 U25_MNUN3$0_drai U25_R1_r1 VSS VSS N L=.50U
> > + W=54.00U
> > M81 PAD U25_R2_r2 U25_MNUN3$1_drai VSS N L=.50U
> > + W=54.00U
> > M82 PAD U25_R2_r2 U25_MNUN3$0_drai VSS N L=.50U
> > + W=54.00U
> > R77 U25_R1_r1 VSS 1.2000K $[NW]
> > R78 VDD U25_R2_r2 1.2000K $[NW]
> >
> > .END
> >
> >
> > --------------404E71479D4--
> >
> >
>
Received on Tue Mar 16 11:35:35 1999