FW: Diode Modeling in SPICE

Silvia -

Diode models are notoriously poor at covering both forward and reverse
directions.

Main things to play with are series resistance RS and breakdown
characteristics (BV and IKV). Tune RS to get a better fit in the forward
direction. Then the breakdown characteristics can be tuned to get a
better fit in the reverse direction.

If the diode goes into forward punchthrough (junction reaches entirely through
a bulk layer), you may need to do more than this. That doesn't sound likely
here.

Lynne Green
HyperLynx

-----FW: <D03DC0494403D1118AB500A02461E687019E2004@sv-msg-01.amer.actel.c-----

Date: Thu, 13 May 1999 16:50:24 -0700
From: "Montoya, Silvia" <Silvia.Montoya@actel.com>
To: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: Diode Modeling in SPICE
Cc: "Montoya, Silvia" <Silvia.Montoya@actel.com>

Hello IBIS model makers !

   I have a 5V CMOS I/O tristate-able buffer I'm trying to model. The IBIS
curves generated by s2ibis2 are a very good match
   to measured data between 0.7v up to about 5.9v. But between -5V to 0.7v
and 5.9v to 10v the curves deviate quite a bit.
   I've disabled the parasitic diodes in the nmos and pmos device models (
IS=0 ) and added n+ and p+ parasitic diodes to the
   netlist. I've been playing with the n+ and p+ diode model (level 3)
parameters ( n, js, ivb, area, pj ) trying to match SPICE
   results to measured data with limited success.

   Are there any suggestions for other model parameters to tweek, or maybe
there is something going on with the s2ibis2 SPICE
   sim limits/parameters I'm not aware of ?
 
  Thanks,
  The time you spend helping me out is greatly appreciated !

   Silvia Montoya
  email : silvia.montoya@actel.com

--------------End of forwarded message-------------------------

----------------------------------
E-Mail: Lynne Green <green@wolfenet.com>
Date: 15-May-99
Time: 11:56:01

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Received on Sat May 15 12:07:34 1999