RE: Subtracting clamp curves from pull-up/down curves

I have a curiosity question. What are the equations that describe the
current in the drain of a FET when Vds is negative for the n channel device
or Vds is positive for the p channel device? I would like to know what the
drain current is, not the current in the diode. I don't believe some of the
equations I have seen.

Tom Dagostino
IBIS and Tau Modeling Manager
BSD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com

-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
Sent: Thursday, July 20, 2000 1:43 PM
To: 'Al Davis'
Cc: ibis-users@eda.org
Subject: RE: Subtracting clamp curves from pull-up/down curves

>From a few weeks ago....

Regarding "the comment":

>When you subtract, remember to consider the accuracy of the
>measurements. In the usual case, in the region where the clamp is
>strong, the things you are subtracting are nearly equal and large,
>producing a result near zero. In most models, the
>resulting pullup/pulldown in this region is ALL NOISE. Those models
>that look like they have a negative resistance region there are
>WRONG. The literature says that it doesn't matter because they are
>added back by the simulator, but that is not the whole story. You are
>better off leaving these points out, even if it means not going the
>full -Vcc to +2*Vcc.
>
>So ...
>Look at the curve! Does it make sense? At the ends, where the curve
>looks like nonsense, throw those points away. Those warnings from
>the parser about "non-monotonic" are real.

I don't entirely agree, or maybe I don't see your point. Non-monotonicity
only matters for the total current, after the individual tables have been
summed together again. If the total current is monotonic, but one of the
component curves isn't, it shouldn't really matter, should it? Unless the
simulator uses the non-monotonic curve by itself somehow. But you know more
about simulators than I do, so maybe you know something I don't.

OTOH, I doubt it hurts to smooth out (not LEAVE out!) those points, as long
as they really are "noise" and insignificant compared to the stronger clamp
current.

Regarding "the question":

>What should a simulator do with the clamps in the region where the
>other clamp applies?
>
>Extend flat? (constant current) -- sure, if it is 0. What if it
>isn't? The current at the splice is double counted.
>
>Make it 0? -- what if they don't match? The currents might not
>match. There might be a gap or overlap. (Consider min or max with a
>different reference voltage.)
>
>Extend last slope? -- this makes sense totally outside, but not here.

Yes, this has bothered me for a while.

Personally, I think that all four curves ... Pullup, Pulldown, and both
Clamps ... should be defined in all IBIS models for I/O (pin) voltages over
the range from GND-POWER to POWER+POWER ... the whole works. This would
force model makers into thinking about how to cut (and how the simulator
will splice) their two clamp currents. The clamp tables might be zero over
half or more of this range, but far better to have it specified that way in
the IBIS data sheet, than to leave it up to chance, or to what the simulator
happens to do with a truncated table.

The mere fact that a table ends anywhere between GND-POWER and POWER+POWER,
is very troubling. What if the current hasn't fallen smoothly to zero where
the table ends?

Regards,
Andy
Received on Thu Jul 20 13:58:06 2000