RE: measuring c_comp using simulation

Hi Arpad,
 
Thanks very much for your input.
 
Just to clarify: I should do the c_meter simulation twice:
1) low temp, high voltage, fast process - use minimum number
2) high temp, low voltage, slow process - use maximum number
3) average between 1 and 2 for typical value
 
I'm not clear on what you mean by "edge rate". In your simulation, your
ramp up was 10ns and ramp down was 10ns. Is that what you refer to as edge
rate? Do you mean to set the edge rate to be close to that of the output
signal driven by the buffer?
 
One final question. Why can't we use the CAPTAB option in Spice to find out
the capacitance at the buffer output node?
 
Thanks,
Betty

-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@intel.com]
Sent: Wednesday, November 29, 2000 6:03 PM
To: 'Betty Luk'; 'ibis-users@eda.org'
Cc: Muranyi, Arpad
Subject: RE: measuring c_comp using simulation

Betty,
 
I am not sure what you mean by "my buffer" and "example", but if
your buffer is a different design from what I used in the lab
exercises, I wouldn't be surprised that the input capacitance
is different. However, I don't think that you would expect them
to be the same, so I feel I have to look for a better answer.
 
I just looked up my lab example's result file "c_meter.mt0" and
got the following data:
 
    capv sw_i1 sw_i2 cap temper alter#
 
    0. -7.947e-04 8.069e-04 1.335e-12 25.0000 1.0000
    0.2500 -1.182e-02 -9.822e-03 1.666e-12 25.0000 1.0000
    0.5000 -2.149e-02 -1.903e-02 2.045e-12 25.0000 1.0000
    0.7500 -2.985e-02 -2.692e-02 2.442e-12 25.0000 1.0000
    1.0000 -3.699e-02 -3.358e-02 2.841e-12 25.0000 1.0000
    1.2500 -4.297e-02 -3.910e-02 3.230e-12 25.0000 1.0000
    1.5000 -4.786e-02 -4.354e-02 3.600e-12 25.0000 1.0000
    1.7500 -5.173e-02 -4.700e-02 3.943e-12 25.0000 1.0000
    2.0000 -5.464e-02 -4.955e-02 4.249e-12 25.0000 1.0000
    2.2500 -5.665e-02 -5.124e-02 4.512e-12 25.0000 1.0000
    2.5000 -5.781e-02 -5.207e-02 4.777e-12 25.0000 1.0000
    2.7500 -5.801e-02 -5.232e-02 4.742e-12 25.0000 1.0000
    3.0000 -5.801e-02 -5.259e-02 4.522e-12 25.0000 1.0000
    3.2500 -5.800e-02 -5.286e-02 4.280e-12 25.0000 1.0000
    3.5000 -5.796e-02 -5.314e-02 4.015e-12 25.0000 1.0000
    3.7500 -5.791e-02 -5.342e-02 3.737e-12 25.0000 1.0000
    4.0000 -5.783e-02 -5.367e-02 3.467e-12 25.0000 1.0000
    4.2500 -5.771e-02 -5.380e-02 3.259e-12 25.0000 1.0000
    4.5000 -5.765e-02 -5.389e-02 3.128e-12 25.0000 1.0000
 
from which the minimum is 1.335 pF and the maximum is 4.777 pF.
These values are clearly different from what is shown in the
plot in my presentation. Looking at the dates I may have
corrected something in the lab examples since I prepared that
plot for the presentation, or changed the buffer, or something.
I also noticed that I did not use the results of the c_meter
simulation for the IBIS files in the "solved" directories,
which may cause even more confusion. I must have been in a big
hurry when I did those, but the point of preparing those files
was not really to have correct content in them, it was just to
have something so that my class attendees should be able to go
on to the next step in case they were not able to get that far.
Please do not get hung up on these differences.
 
To give you an answer to which number to use, here is the rule I use:
Take the lowest number generated with the c_meter simulation file
with the fast corner conditions (usually low temp, high voltage,
fast process) and use it for the minimum C_comp, and take the
highest number from the c_meter simulation using the slow corner
conditions (high temp, low voltage, slow process). Average the
two for the typical value for C_comp.
 
It is important that you only sweep the chip on that voltage range
which corresponds to the signal swing. For example, if you have a
3.3 V device with a GTL buffer, don't sweep it 0 to 3.3 V to obtain
the capacitance curve, sweep it only between 0 to 1.5 V. The signal
will never see the capacitance values that would occur on other
voltages.
 
Also note that the edge rate at which you sweep the buffer may also
influence the results you get. It would be advisable to set an edge
rate in the c_meter simulation which is similar to what the buffer
will see from the signal.
 
I hope this helps,
 
Arpad Muranyi
Intel Corporation
=====================================================================
 
 
 
-----Original Message-----
From: Betty Luk [mailto:Betty@genesis-microchip.com]
Sent: Wednesday, November 29, 2000 11:33 AM
To: 'ibis-users@eda.org'
Cc: 'arpad.muranyi@intel.com'
Subject: measuring c_comp using simulation

Hi,
 
In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
website), there was a sample Spice netlist for a simulation to obtain the
value of c_comp. When I used this simulation for my buffer, the capacitance
ranged from 2pF to 8pF, with a mean of 5pF. In the example, the range was
only between 2 to 3pF. Should the mean value for the simulated capacitance
be used? What about obtaining min and max values for c_comp?
 
I would really appreciate any feedback. I have attached the sample Spice
file for reference.
 
Thanks very much,
Betty
 
 

 
Received on Thu Nov 30 06:45:21 2000