Re: On chip Active termination

Dear Prasad Rau,

Might I suggest that you ask technical support for the HyperLynx products at
support@hyperlynx.com or (425) 869-2320?

Best regards,
Matthew Flora

----- Original Message -----
From: "Prasad Rau" <prasad.rau@xilinx.com>
To: <ibis-users@eda.org>
Sent: Friday, April 13, 2001 5:57 PM
Subject: On chip Active termination

> Hi,
>
> On our current design we support several standards using controlled
impedance. By using this scheme
> we can mimic driver or receiver end terminations for standards like
SSTL,HSTLs
> and GTL. The onchip termination is done using active devices as opposed to
passive
> elements. For example in the SSTL2 Class I the parallel termination is at
the receiver end.
> Using the controlled impedance scheme we can eliminate the series & parallel
termination resistor son the board.
> I have created seperate IBIS models for the output and the input. When I use
the output model
> and drive the input model through a Tline using the HyperLynx tool I am not
seeing the right
> levels at the receiver end. It is telling me that the termination at the
receiver is missing. I know
> that the input IBIS model makes sense because if I look at the GND clamp
curve I observe ~ 0mA
> current at 1.3V ( which is the valid voltage level with the output
tristated). The same driver model
> if it drives a non controlled impedance receiver with the appropriate board
termination at the receiver
> gives me the correct levels at the receiver.
>
> Is HyperLynx unable to recognize onchip termination input IBIS models ? Has
aynone
> worked with controlled impedance and have suggestions in modelling them in
IBIS.
>
>
> Appreciate your help in this regard.
>
>
> Thanks in advance,
>
>
> Regards,
>
> Prasad Rau
> Xilinx
>
>
>

 
Received on Sat Apr 14 11:01:09 2001