On chip Active termination

Hi Stephen,

Thanks for your feedback. My intention was to make sure I was not
making a modelling mistake before I questioned the tool. I should have
perhaps, framed my questions differently. My apologies to the IBIS
community.

Regards,

Prasad

"Peters, Stephen" wrote:

> Hi Prasad:
>
> If by 'controlled impedance' you mean builing termination resistors or
> clamps on die then yes, IBIS does support this. Simply include the on die
> termination in the circuit when extracting the I/V data for the [Gnd Clamp]
> or [PWR Clamp] curves.
>
> Also, everyone please note that for vendor specific tool questions you
> should contact the vendor directly. Per EIA policy, the ibis-users and ibis
> reflectors are for IBIS related discussions only.
>
> Regards,
> Stephen Peters
> Intel Corp.
> Vice Chair, EIA/IBIS Open Forum
>
> -----Original Message-----
> From: Prasad Rau [mailto:prasad.rau@xilinx.com]
> Sent: Friday, April 13, 2001 5:58 PM
> To: ibis-users@eda.org
> Subject: On chip Active termination
>
> Hi,
>
> On our current design we support several standards using controlled
> impedance. By using this scheme
> we can mimic driver or receiver end terminations for standards like
> SSTL,HSTLs
> and GTL. The onchip termination is done using active devices as opposed to
> passive
> elements. For example in the SSTL2 Class I the parallel termination is at
> the receiver end.
> Using the controlled impedance scheme we can eliminate the series & parallel
> termination resistor son the board.
> I have created seperate IBIS models for the output and the input. When I use
> the output model
> and drive the input model through a Tline using the HyperLynx tool I am not
> seeing the right
> levels at the receiver end. It is telling me that the termination at the
> receiver is missing. I know
> that the input IBIS model makes sense because if I look at the GND clamp
> curve I observe ~ 0mA
> current at 1.3V ( which is the valid voltage level with the output
> tristated). The same driver model
> if it drives a non controlled impedance receiver with the appropriate board
> termination at the receiver
> gives me the correct levels at the receiver.
>
> Is HyperLynx unable to recognize onchip termination input IBIS models ? Has
> aynone
> worked with controlled impedance and have suggestions in modelling them in
> IBIS.
>
> Appreciate your help in this regard.
>
> Thanks in advance,
>
> Regards,
>
> Prasad Rau
> Xilinx

 
Received on Mon Apr 16 11:12:44 2001