Re: about the IBIS "checklist.txt."

Dear LiuWeidong,

Please see my answers below your questions. I hope this helps you.

Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

"LiuWeidong" <liuweidong@huawei.com> on 07/23/2001 08:38:09 PM

To: Gregory R Edlund/Rochester/IBM@IBMUS
cc: <ibis-users@eda.org>, <ibis@eda.org>
Subject: about the IBIS "checklist.txt."

Hello, Greg
I have some questions about your IBIS Datasheet Checklist :

"3. Has the modeling engineer performed a visual inspection of IV and VT
curves to screen for non-monotonicity, discontinuities, and other obvious
errors?"
If a IV curves is non-monotonicity,How can I deal with it ? Can the model
be used by the simulation tools?
There are so many IBIS models provided by IC venders whose IV curves is
non-monotonicity .

[GREG] Non-monotonicity can be OK in some circumstances. Page 20 of the
IBIS Cookbook shows an example of a pull-down curve that becomes
non-monotonic after you subtract out the ground clamp current (I believe
this is a numerical effect). Once you add the two curves back together,
the composite becomes monotonic again, so this is OK. In other
circumstances non-monotonicity may be indicative of a circuit feature such
as bus hold, which uses a feedback circuit. This can make the simulator
fail, so I usually smooth out the non-monotonicity in the IV curve of a
circuit that has bus hold. The point is that you need to know what's
causing the non-monotonicity. Your IBIS vendor should do this for you.

"8. Does the output reach Vmeas under standard load conditions for rising
and falling waveforms?"
For this item , I don't think it should be in the IBIS Datasheet Checklist
, Whether the output can reach Vmeas under standard load conditions for
rising and falling waveforms mainly depend on the output buffer's driving
capability . If a buffer's driving capability is very weak, the output
maybe can't reach Vmeas under standard load conditions for rising and
falling waveforms,but you can't think the IBIS model is wrong.

[GREG] Vmeas comes from the component datasheet, and so the output better
be able to drive it's own standard load. If it can't, there's something
seriously wrong with the circuit design. If the behavioral simulations
using the IBIS file don't reach Vmeas with the standard load but the real
component DOES, then something went wrong during the creation of the IBIS
file.

Hope for your reply!
Thanks!
LiuWeidong

----- Original Message -----
From: Gregory R Edlund <gedlund@us.ibm.com>
To: <Anbu@scmmicro.co.in>
Cc: <ibis-users@vhdl.org>
Sent: Thursday, May 24, 2001 8:53 PM
Subject: Re: Clarification needed.

>
> Anbazhagan,
>
> Looks like you're on the right track. I would recommend your ASIC vendor
> read the "IBIS Cookbook," which can be found on the IBIS web page:
> http://www.eigroup.org/ibis/tools.htm
>
> As part of the "I/O Buffer Accuracy Handbook" (also available on the IBIS
> web page), we published a checklist that should help you. This list was
> compiled from suggestions by members of the SI community who have
> experience with IBIS. I am attaching the most recent version of this
list.
>
> Bob, Could you please post this list as an ASCII text file under
Accuracy?
> Pleas name it "checklist.txt." Thanks.
>
>
> IBIS Datasheet Checklist version 1.1,
> 05/07/01
> ------------------------
>
>
> IBIS datasheet:
> Component manufacturer:
> Component part number:
> Engineer verifying this component:
> Email address:
> Behavioral simulator and version:
> Date:
>
>
> Note: If answer is N or N/A, provide explanation.
> The user may verify items 1-9 but is unable to verify items 10-20
> because the data involved are only available to the semiconductor
> vendor.
>
>
> ___ 1. Does the IBIS datasheet pass the IBIS syntax checker?
> (Note: Some models generate warnings for non-monotonicities that
> are
> actually part of the characteristics of the device. Other non-
> monotonicities are so small as to be irrelevant.)
>
> ___ 2. Is an "I/O Buffer Accuracy Report" available for this component?
> (http://www.vhdl.org/pub/ibis/accuracy)
>
> ___ 3. Has the modeling engineer performed a visual inspection of IV and
> VT
> curves to screen for non-monotonicity, discontinuities, and other
> obvious errors?
>
> ___ 4. Has the modeling engineer tested the IBIS datasheet using a
> behavioral
> simulator?
>
> ___ 5. Do MIN and MAX data exist for all keywords and sub-parameters?
>
> ___ 6. Does the IBIS datasheet include all four 50 Ohm VT tables as
> described
> in the IBIS Cookbook?
>
> ___ 7. Do the keywords Cref, Rref, Vref, and Vmeas match the values
> specified
> in the component datasheet for all output and bidirectional
models?
>
> ___ 8. Does the output reach Vmeas under standard load conditions for
> rising
> and falling waveforms?
>
> ___ 9. Does the pin table match the component datasheet?
>
>
> ___ 10. Do the keywords Vihl and Vinh represent the unity gain points
> derived
> from the dc transfer characteristics for all inputs?
>
> ___ 11. Has the modeling engineer verified the accuracy of the C_comp
> subparameter?
>
> ___ 12. Has the modeling engineer verified the accuracy of the R_pkg,
> L_pkg,
> and C_pkg subparameters?
>
> ___ 13. For CMOS logic, do all MAX data represent maximum voltage,
minimum
> temperature, and fast process?
>
> ___ 14. For CMOS logic, do all MIN data represent minimum voltage,
maximum
> temperature, and slow process?
>
> ___ 15. For bipolar logic, do all MAX data represent maximum voltage,
> maximum
> temperature, and fast process?
>
> ___ 16. For bipolar logic, do all MIN data represent minimum voltage,
> minimum
> temperature, and slow process?
>
> ___ 17. Do the keywords dV/dt_r and dV/dt_f contain the correct 20%-80%
> edge
> rate data measured using a 50 & load as specified in IBIS?
>
> ___ 18. If the I/O buffer employs dynamic clamping, does the IBIS
datasheet
> contain the appropriate keywords and subparameters?
>
> ___ 19. If the I/O buffer employs a multi-stage driver, does the IBIS
> datasheet
> contain the appropriate keywords and subparameters?
>
> ___ 20. If the I/O buffer design employs dynamic edge rate control,
dynamic
> impedance control, or any form of feedback, has the modeling
> engineer
> assessed the impact of this circuitry on behavioral model
accuracy?
>
>
> Greg Edlund
> Electrical Packaging
> IBM Server Technology Development
> 3605 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> gedlund@us.ibm.com
>
>
> Anbu@scmmicro.co.in on 05/24/2001 01:48:13 AM
>
> To: "ibis-users@eda.org":
> cc:
> Subject: Clarification needed.
>
>
>
> Hello Users,
>
> I am using XTK to simulate a PCBA. The board has a 100pin ASIC.
In
> order to model the ASIC properly I need the IBIS model of the ASIC which
I
> can convert it to XTK format. Now if I directly request for an IBIS model
> the vendor may hesistate. So I am requesting the following data from the
> vendor with which I can create a IBIS model. Below is the data I am
> requesting them. Is it OK. Does it cover everything necessary to create a
> proper IBIS model?. The ASIC does not have any clamp diodes. Please
reply.
> The following data whichever is applicable for each pin of the ASIC are
> needed
> 1. Package parasitics namely, the Resistance, capacitance and
Inductance.
> Typical, max, min values required.
>
> 2. Die capacitance as seen at the die pad. Typical, max, min values
> required
>
> 3. Output impedance of the I/O buffers. Typical, max, min values
required.
>
> 4. Rise time and fall time values (dv/dt typical, max, min) of buffers
> excluding the effect of packaging but including the effect of die
> capacitance. Load conditions required.
>
> 6. Rising edge and falling edge waveforms (Voltage vs. time curve with
the
> voltage values having typical, max, min values) of the driver along with
> the test conditions.
>
> 5. V/I characteristics of Pull up and Pull down resistor, if present,
when
> the buffer is driven high and low respectively. The voltage sweep must be
> from ?3.3V to +6.6V. Current measurement with typical, max, min values
are
> required.
>
> Thanks,
>
> Anbazhagan.
>
>
>
>
>
>

 
Received on Wed Jul 25 06:50:29 2001