Re: How to determine per length RLC in a board

Yaping,

In the SIG-GND-PWR, the PWR plane is not a return path for the signal
layer. I suggest you model it as SIG-GND (microstrip). The high-speed
currents will always use the GND plane, assuming good decoupling between
PWR and GND.

Alan

Yaping Zhou wrote:
>
> Hi, All:
>
> If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
> the characteristic impedance is the same for switching high and low, and the
> per length RLC are also the same for both switching cases.
>
> How to determine the per length RLC in a board with a stackup like
> SIG-GND-PWR? The characteristic impedance and per length RLC are
> switching-dependent, but there is no way to put two values for each trace in
> an ebd file.
>
> Intel uses ebd to describe packages used for Pentium processors,I have the
> same question there on the way to determine RLC values.
>
> Your help is appreciated.
>
> Thanks,
>
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