RE: How to determine per length RLC in a board

Vinu,

I was refering to high speed degigns where the package and die (and bus)
were designed for GND-SIG-PWR. In any case, you should do return path
analysis for specific high speed buses with product constraints. There are
no general rules because there are no general boards.

... Rich

-----Original Message-----
From: Vinu Arumugham [mailto:vinu@cisco.com]
Sent: Wednesday, June 06, 2001 2:26 PM
To: Mellitz, Richard
Cc: ibis-users@eda.org
Subject: Re: How to determine per length RLC in a board

Rich,

I am assuming a SIG-GND-PWR package stack-up and a board stack-up that may
be 4
to say 20 layers (not GND-SIG-PWR). Boards usually have one to several
ground
planes and a few power planes. With the number of different power supply
voltages on current boards, power planes tend to be split up into islands or
are implemented as shapes on surface layers. Hence power structures tend to
be
poor references for signals and most routing is referenced to ground. Even
if
signals were referenced to power planes, the plane voltage may not be the
same
as PWR on the package. My bump pattern recommendation was based on the
above.

Thanks,
Vinu

"Mellitz, Richard" wrote:

> Vinu,
>
> PWG and GND bumps distributed within the signal bumps pattern minimizes
the
> non TEM discontinuity impact of the return structure of a GND-SIG-PWR
board
> stackup. Doesn't this sound good in theory? :-) You need to return the
> current induced on all planes. One of those energy things 'ya know. Any
> thing that is non TEM can be models with a lumped mesh. What you find out
> when you do this is that you must add more on die PWR decoupling if the
PWR
> bumps are in the center of the BGA. This is especially true if IO PWR is
not
> the same as CORE power. 'Gotta keep core happy too, but that's another
> story. Of course you may be talking about a wire bond package... which
has
> another set of challenges. :-( In short, there is no general best way.
There
> are always trade offs. The challenge is to put good analysis data behind
the
> decision.
>
> One simple approach is to model TEM structures with transmission lines and
> non TEM with PEEC meshes and hope you can figure out how to ground the
whole
> mess so you don't have convergence problems. Then you can simplify and
guard
> band the bounding cases in ground referenced black boxed equivalent
circuit
> TEM simulation and be kind to your customers. ... enter stage right...
IBIS.
> It doesn't always work, but that's the challenge. :-)
>
> ... Rich
>
> -----Original Message-----
> From: Vinu Arumugham [mailto:vinu@cisco.com]
> Sent: Tuesday, June 05, 2001 4:47 PM
> To: Yaping Zhou
> Cc: Alan Hilton-Nickel; ibis-users@eda.org
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> The recommended bump pattern for the SIG-GND-PWR package stackup would be
as
> follows:
>
> GND bumps distributed uniformly throughout the package.
> PWR bumps only at the center (area BGA) or only on the inner periphery
> (perimeter BGA).
>
> With the above pattern, since you have only one signal layer, the return
> current will always flow on the nearest plane (GND in this case) even when
> there is no decoupling capacitance on the chip/package between PWR and
GND.
>
> If the PWR bumps are distributed over the entire package, it gets
> complicated.
> PWR-GND decoupling on the package may be important (depends on the
> stack-up/routing/decoupling on the board on which the BGA is mounted). In
> any
> case, the impedance will be independent of the signal transition
direction.
>
> Thanks,
> Vinu
>
> Yaping Zhou wrote:
>
> > Alan & Vinu:
> >
> > Thank your for your reply.
> >
> > I am actually interested in package modeling, is "good decoupling"
usually
> a
> > good assumption in high-speed devices with a limited on-chip decoupling
> > capacitance?
> >
> > Yaping
> >
> > ----- Original Message -----
> > From: "Alan Hilton-Nickel" <ahilton@transmeta.com>
> > To: "Yaping Zhou (r3aadv)" <y.zhou@motorola.com>
> > Cc: <ibis-users@eda.org>
> > Sent: Tuesday, June 05, 2001 12:26 PM
> > Subject: Re: How to determine per length RLC in a board
> >
> > Yaping,
> >
> > In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> > layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> > currents will always use the GND plane, assuming good decoupling between
> > PWR and GND.
> >
> > Alan
> >
> > Yaping Zhou wrote:
> > >
> > > Hi, All:
> > >
> > > If the stackup in a board is a symmetric stripline structure
> > (GND-SIG-PWR),
> > > the characteristic impedance is the same for switching high and low,
and
> > the
> > > per length RLC are also the same for both switching cases.
> > >
> > > How to determine the per length RLC in a board with a stackup like
> > > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > > switching-dependent, but there is no way to put two values for each
> trace
> > in
> > > an ebd file.
> > >
> > > Intel uses ebd to describe packages used for Pentium processors,I have
> the
> > > same question there on the way to determine RLC values.
> > >
> > > Your help is appreciated.
> > >
> > > Thanks,
> > >
> > > --
> > > **************************************
> > > Yaping Zhou (r3aadv)
> > > (512) 933-5803
> > > Motorola Semiconductor Products Sector
> > > Final Manufacturing Technology Center
> > > Ed Bluestein, Austin, Texas
> > > **************************************

 
Received on Wed Jun 6 14:36:09 2001