(no subject)

 Hi,

We have two approaches to model LVDS:

- The first one:
         - The normal wave form will be included in this approach.(Generated
by Rload to Vref on both +ve and -ve PINs)
         - Operating point analysis with variable Rload to the same Vref
will generate the pull up/down.

This approach is a Global one; you can use it for any differential buffer
with whatever differential load (linear or non-linear). Because you extract
the V-I data in actual buffer operation.

By using this approach you got an IBIS model with the differential resistor
behavior embedded inside the model.

The second one:
       - You begin by extracting the differential load value (or if it is
stated in the data sheets)
       - If it is a linear resistance so you can go on in this approach, if
not you go back to the first one.
       - Extract the waveform and the DC curves by the setup stated in the
presentation.

We have now differential load decomposed IBIS model for that buffer. So you
should add the differential resistor to you model by series resistor element
to get the original behavior.

I hope that helps,
BR,

-----Original Message-----
From: Hirut Asfaw
To: ibis-users@eda.org
Sent: 6/15/01 7:01 PM

Hi Folks,
     A question regarding *LVDS* I/Os with internal terminations between
the diff pins.
          When characterizing the Series resistance between the diff
pins,
is the intention to capture the current prior to IBIS generation.
Meaning,
is this part of Spice set up before the IBIS model is generated? or can
we
just include this resistance (as a physical) model once the IBIS model
is
genrated?

Thanks,
Hirut

Hirut Asfaw
ASIC I/O Developement
IBM Microelectronics Division
External: (802) 769-0652 T/L: 6-0652
hasf@us.ibm.com

 
Received on Fri Jun 15 16:12:01 2001