RE: ibis usage for timing diagrams

> 1. Should I be able to verify a value given in the data sheet with the
> ibis model?
 
No. IBIS "models", like most SPICE models, represent only a portion of the
IC. A SPICE model usually includes only the output buffer. The IBIS
"model" simulates nothing more than the output characteristics (for output
pins). Nothing else in the IC is included. There is no "clk".

Either representation should produce a reasonable facsimile of the output
waveforms, under varying load conditions, but there is no absolute timing
information. All the timing is relative.

What you would do, is simulate with your IBIS model connected to the spec
sheet's test load, find the time where the output waveform crosses whatever
voltage they used to measure the spec sheet's delay, and then use that as a
reference when you try different loads.

For example, if the spec sheet says the clk-to-output delay is 4.5 ns when
the falling edge crosses 0.8V, take the point where your simulator shows the
falling waveform crossing 0.8V, and re-calibrate your time axis so that you
now call that point "4.5 ns." Then simulate using the circuit you want, and
see how the delay differs from that with the test load.

When the vendor's spec sheet information is incomplete or faulty, you are
out of luck as far as absolute timing is concerned. (But if it's a standard
logic family, there may be conventions that you can use that aren't stated
on each data sheet.) Regardless, you can still simulate to get waveforms,
and compare their timing to whatever "standard" test load you choose.

Regards,
Andy

 
Received on Tue Mar 20 14:19:09 2001