RE: another C_comp confusion question

Aha! Another good reason to use the "I/O Buffer Accuracy Handbook!"
(Sorry, I helped write this, and I couldn't resist.)

5 pF doesn't sound terribly high for an output. Inputs seem to be around
2-3 pF (mostly ESD devices, I think). I like to use a TDR to measure
device pin capacitance. There's a reference on how to do this in the above
doc. Of course, a user would rather not worry about this, right? That's
why putting model accuracy in a purchase spec is such a good idea -
although easier said than done. When we worked with one vendor on this,
they were very cooperative. The key is finding the person who does the
modeling and talking to him or her directly.

0.162 pF seems way too small. I've never seen a device with a capacitance
this small. At any rate, the simulator should not blow up. Sounds fishy.
Note that the model developer has to enter this value "by hand" if he or
she is using the SPICE-to-IBIS converter. The converter does not extract
C_comp automatically. This makes the parameter susceptible to boo-boos or
just plain oversight.

C_comp information is contained in the VT tables, but a good simulator will
back out the effects of C_comp before creating its internal stimulus
functions. (People like to call this process "de-embedding.") You still
need the C_comp capacitor in your simulation model to accurately account
for what happens when a reflection hits the driver.

I would recommend getting VT tables added to the IBIS file if possible.
They allow you to account for things like pull-up and pull-down devices
switching at slightly differenent times, which can be an accuracy
enhancement.

By the way, the best list for these questions is: ibis-users@vhdl.org

Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com
---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
05/16/2001 12:12 PM ---------------------------

Bob Khederian <RKhederian@whiteedc.com> on 05/16/2001 09:50:46 AM

To: "'Wilco Hamhuis'" <w.hamhuis@transfer.nl>, Ibis <ibis@eda.org>
cc:

Subject: RE: another C_comp confusion question

Hi All,

I have also had a problem with Ccomp, but the other extreme. I have seen
Ccomp values of 5pF. Recall according to the IBIS spec, "Ccomp defines the
silicon die capacitance". I find it difficult to beleive that the
capacitance of a die (we deal with memory here) is 5pF. Has anyone had
similar concerns? Has anyone addressed this with any of the silicon
vendors?

Bob.

-----Original Message-----
From: Wilco Hamhuis [mailto:w.hamhuis@transfer.nl]
Sent: Wednesday, May 16, 2001 9:40 AM
To: Ibis
Subject: another C_comp confusion question

Hi all,

Betty Luk initiated this topic a few months ago. Recently I received a
differential IBIS model from a vendor. I noticed that the C_comp value was
very small, 162fF. Apparently the C_comp value is also included in the VT
tables. In my case I don't have the VT tables. The driver model only
consists out of the pullup and down curves. Gnd, power, rise and fall
aren't
present (ramp data is present). When I use this model in a XTK simulation I
see very large oscillation, straight through the logic threshold levels.
Increasing the C_comp value a bit and the results become significant
better.
I find it VERY disturbing that C_comp has such a large impact on the
simulation results. My questions:

 - is 162fF a realistic C_comp value according to your experience?
 - does anyone have any experience with questionable simulation results due
to C_comp value?
 - what is the relationship between the VT tables and C_comp?

Tanks in advance,

Wilco
Signal Integrity Expert

 
Received on Wed May 16 10:36:55 2001