Re: [IBIS-Users] Questions about Bus Hold (2nd try)


Subject: Re: [IBIS-Users] Questions about Bus Hold (2nd try)
From: Ross, Bob (bob_ross@mentorg.com)
Date: Thu Nov 21 2002 - 14:45:06 PST


Rob:

I am going to try to address your questions directly based
on what I have seen in some Philips models and Philips modeling
processes.

Ironically, the primary reason for bus_hold was to document a
receiver triggered switching circuit to give extra strength at
the receiver from a weak driver. This circuit performed just
like a bus hold circuit, but with much stronger currents. Because
it was a similar effect as bus hold, it was named bus hold.

As a general rule, for most modeling situations, the true
bus hold effect can and should be ignored. What commonly
occurs in s2ibis typ extractions is that the [Gnd Clamp]
table is non-monotonic in the 0 to Vcc region, with a
negative and then positive glitch around approximately
Vcc/2 - corresponding to a bus hold circuit switching
during the DC sweep. However, this current is negligable
with respect to overall signal integrity and timing
considerations and can be ignored. Most tools have
loads on the net (including the characteristic impedance
of the traces) that swamp out the non-monotonic effect
during switching, so it is no factor. Other tools may
smooth out the glitch.

My responses are in your text.

Bob Ross
Mentor Graphics

rob.mataheroe@philips.com wrote:
>
> Hello Ibis collegues,
>
> I want to make accurate IBIS models for input buffers and I/O buffers with bus hold.
> Existing models, I have seen on the web, show the bus hold characteristic in the ground clamp curve.
> When running the IBIS checker, this causes non-monotonic warnings.
> Therefore I am not sure whether this way of modeling is correct.

My recommendation is to simply zero out the clamp currents and remove
the glitch - for the purpose of correct simulation and removal of
warning messages (versus exact characterization). If needed, put in
the full bus hold submodel statements.

>
> This brings me to the following questions:
>
> 1. If the bus hold characteristic is present in the ground clamp curve, how would you qualify this:

> 1a Wrong, since it causes non-monotonic warnings

It is correct as far as a DC sweep and approximation effect is
concerned. However, see 1b, 1c

> 1b. Useless

Probably not needed for most situations. A 75 uA current is
negligable compared to mA level switching current flows, and
it is zero at the end-points anyway where circuits tend to
settle.

> 1c. Okay, since it represents the actual behavior.

It mimics actual behavior through only a DC sweep mechanism.
However since the mechanism is dynamic (e.g., a flip flop),
the DC characterization is not correct. So the correct
approach is to zero out the currents. If you really want
it, use the true submodel characterization based on switching.
See 1a :-)

> 1d. Other ....

True Bus Hold submodel. Plus 1b for many real situations.

>
> 2. The IBIS standard describes the Bus Hold Submodel.
> I assume the Top Model describes the buffer without bus hold characteristic.
> From the IBIS standard I cannot understand what part of the circuit I must simulate in order to gather the data for the Bus Hold Submodel, namely the pullup, pulldown and last but not least the ramp figures.

The bus hold requires internal knowledge for construction. Basically
the strength of the bus hold pullup and pulldown "resistors" are needed,
and the speed of transition is needed, and the approximate switching
thresholds are needed. I recommend just a very simple model with ramps
since the effect is already on top of more dominant effects. So the
bus hold serves as a first order adjustment. When a real internal
switch is characterized with mA level strength, then more detail is
needed. However, the Semiconductor manufacturer modeler should have
access to the necessary details including the bus hold circuit itself.

>
> Of course those who have designed the IBIS standard must know the idea behind the Submodel.
> Therefore I would appreciate it very much if somebody could tell me:
> 2.1 Which part of the circuit is described by the sub model?

Just the bus hold switch mechanisms.

> 2.2 How can I get more information about this subject?

Let me know if you have further questions.

>
> Thank you in anticipation for your reactions.
>
> Kind regards,
>
> Rob
>
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