Subject: RE: [IBIS-Users] FW:
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Fri Dec 06 2002 - 14:19:53 PST
Eric,
Answers to your questions:
1) We do it all the time.
2) The HSPICE B-element includes the C_comp, so you don't need to
add that to your circuit. The rest are not included in the B-element,
so you will need to add those around it.
Arpad
=====================================================================
-----Original Message-----
From: Eric Hsu [mailto:ehsu@netlogicmicro.com]
Sent: Friday, December 06, 2002 1:40 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] FW:
Hi All,
Is there anyone ever take IBIS mode and spice netlist and use hspice to
simulate on the same environment? I wonder maybe it is the best way to cross
verify correlation between IBIS model and spice netlist. If it is possible,
how can I handle R_pin, L_pin, C_pin, and C_comp those parameter in the
ibis model? I mean should I add them into my test bench or not?
Best Regard,
Eric Hsu
Senior Design Engineer of Interface Technology
NetLogic Microsystems, Inc.
ehsu@netlogicmicro.com
650-961-6676 X198
-----Original Message-----
From: Eric Hsu [mailto:ehsu@netlogicmicro.com]
Sent: Friday, December 06, 2002 11:44 AM
To: 'ibis-users@eda.org'; Arpad Muranyi (E-mail)
Subject:
Hi all and Arpad,
Could you please share your experience about verification spice and ibis
performance correlation? I found on page 8 of the article "I/O-buffer
modeling spec simplifies simulation for high-speed systems"
(http://www.eigroup.org/ibis/intel.htm), there is a figure mention about
spice and ibis waveform comparison. Do you think it was simulated by the
same tool? If it was, what's tool you used here? Or is anyone know what's
the tool I can use? How about like Hyperlynx, Quad Design, or
Interconnectix?
Best Regard,
Eric Hsu
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