[IBIS-Users] V-t curves discussion

Arpad, Bob, Tom, Lynne, Aubrey, Giovanni, Nitin:

    Thanks for your feedback. I agree the delay differences are generated by
the difference of switching thresholds of IBIS model buffer simulated in
HSPICE and transistor model, because to a output buffer implemented with
IBIS in HSPICE its input signal is a digital signal with values 0 and 1,
and its Vinl and Vinh values are 0.2 and 0.8 respectively. This is the
cause!!
    But, there is an additional problem, those threshold differences modify
the duty cycle.
    HSPICE has two keywords that can help to compensate the delay: rwf_scal
and fwf_scal. I have been playing with those keywords and the delay is
compensated but occurs some mismatchs between wave shapes, in the edges of
course; when I shift the V-t tables to compensate de delay this mismatch
doesn't occurs!!
    To the IBIS users the delay doesn't represent a problem because they
don't have a reference to comparate the delay. However the duty cycle is now
the problem because it will be modified if the input stimulus transistion
time is changed.
    Here my questions: Is a IBIS's goal to simulate correctly the duty
cycle?
                       Does PCB engineers need to simulate the correct duty
cycle?
                       Or Is their job more directed to a electrical
phenomenoms (electrical or electromagnetic behavior)?
    If it is necessary to simulate correctly the duty cycle using IBIS then
I have a new problem because I can correct it to use it in HSPICE (in
addition I will have to write notes about valid rise/fall times) but if the
IBIS model is simulated in other tool maybe this correction is not going to
work.

    Thanks.

    Regards,

    Ramiro Rodriguez
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Received on Fri Oct 15 08:51:30 2004