[IBIS-Users] RE: BIRD95: Power Integrity Analysis Using IBIS

Zhiping,

I will just quote your latest response to reduce the
size of this thread.

You raise a good concern. There is room for a lot of
improvements to get IBIS to reproduce the same PD simulation
results as an equivalent SPICE model. However, there are a
lot of features in the existing capabilities of IBIS to
improve the accuracy of IBIS models for SSO simulations,
and many of these are still not utilized in many cases.

You mentioned power to signal coupling, and I would add
power to GND coupling. Not too many people realize that
the primary reason for the additional C_comp parameters
in the 4.0 specification was exactly for this reason
(C_comp_pullup, C_comp_pulldown, C_comp_power_clamp,
C_comp_gnd_clamp). The single C_comp concept didn't
allow for describing such coupling. Another detail that
is not realized many times is that if the total C_comp
is split into two parts, one between the I/O pad and
Vcc and the other between the I/O pad and GND, these
two capacitors will automatically introduce a Vcc to
GND coupling too!

In addition, if this was not enough to model the total
decoupling between Vcc and GND, one can always add
more to it using the already existing series keywords,
which can also be connected between power and GND pins.
This solution is not the most elegant, since it uses
a separate [Model] of type Series, but either way, it
can be done.

Regarding the HSPICE manual, if you can get a hold of
manuals of earlier versions (sorry, but I can't remember
exactly which one has it), you may find a little more
on this. The problem is that the writer of the manual
didn't seem to understand what this does and the equations
are wrong, that is probably why it was taken out...

Anyway, what it does is this: The actual voltage between
power and GND is compared against the value which is in the
IBIS file either in [Voltage Range], or the difference
between the PU and PD reference keywords. If the
instantaneous voltage is different from the nominal value,
the IV curve will be scaled according to the pu_scal or
pd_scal values.

If the "scal" value is 1, the IV curve is scaled by the
same proportion the supply voltage changed. In other
words, a 10% change in the supply voltage will change the
IV curve by 10% also. If the "scal" value is 0, there
will be no change in the IV curves. If it was 0.5, then
a 10% change in the supply voltage will result in a 5%
change in the IV curves, etc... (The value of "scal" is
not restricted to be between 0-1).

I hope that the Synopsys lawyers are not going to chase
after me for publishing this... It is in their advantage
anyway if people know how to use this feature, right?

We all know that due to the second order nature of MOSFETs
this linear relationship is not exact. However, this
scaling is not designed to go all the way down to 0 volts.
In the range of the relatively small modulation this linear
approximation seem to be sufficient. However, if it turns
out that it is not, we can always improve on it by changing
the equations to be more precise.

Arpad
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-----Original Message-----
From: Zhiping Yang [mailto:zhiping@cisco.com]
Sent: Monday, January 10, 2005 12:02 PM
To: Muranyi, Arpad; ibis@eda.org; ibis-users
Subject: Re: [IBIS-Users] Re: [IBIS] RE: BIRD95: Power Integrity Analysis Using IBIS

...

Yes. I understood that some EDA tools could let IBIS to simulate the SSO,
but my concern is that their results may not be correct. Besides the "gate
modulation effect" which we talked about, my personal understanding is that
even the SSO noice can be simulated with exisiting IBIS model, but the noise
coupling mechanism from power to signal pin may not be implemented or not
implemented correctly. In another word, could the power noise impact on the
rising/falling edge in IBIS simulation match to the HSPICE simulation? I
could be wrong and I am working on some simulations in HSPICE to verify it.

...

I just read the HSPICE manual on these two parameters (spu_scal and
spd_scal) you mentioned. I didn't see any detailed explainations on how to
use them. Do you have any examples to show their impact on the IBIS
performance? Personally I feel it may improve the IBIS performance, but it
still can not completely solve the "gate modulation effects" in IBIS.
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Received on Mon Jan 10 12:44:27 2005