RE: [IBIS-Users] VHDL-AMS Model

Hello, Lee,

An excellent question.

VHDL-AMS (and Verilog-AMS) are standards. They support mixed-signal
modeling. One can express a functional block, such as a MUX or I/O buffer,
as a digital, analog, or mixed-signal block. Analog blocks can be expressed
as equations, including if/then controls, which has both advantages over
table-based models (such as taking into account independent variations with
Vcc and Temperature).

Starting with IBIS 4.1, VHDL-AMS, Verilog-AMS, and SPICE 3f5 models are
allowed as model formats for IBIS, under the [Model] keyword. All of these
can be used as behavioral or structural descriptions of a block, such as an
I/O buffer or a MUX. Please see the IBIS 4.1 specification for details.

Best regards,
Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of lee yang
Sent: Sunday, January 30, 2005 9:35 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] VHDL-AMS Model

Hi,

Recently I heard about another behavioral model call VHDL-AMS, can anyone
please give some background about it?
Since we already have IBIS model, what is the reason we need to use VHDL-AMS

model instead? What is the pros and cons compared to IBIS model?
Thanks and appreciate if someone can shed some light.

-Lee Yang

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Received on Mon Jan 31 08:40:25 2005