RE: [IBIS-Users] question on validation with HSPICE

I suspect your problem lies in the fact that you have C_fixture, etc. in the
model.  In the past when I have seen these called out in IBIS models the
simulators had all kinds of issues trying to get good results.

Also, you have end point warnings and errors, they need to be fixed.

Tom Dagostino
Teraspeed Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
http://www.teraspeed.com
tom@teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of CW - Doran David
Sent: Thursday, March 03, 2005 12:09 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] question on validation with HSPICE


Hello experts :

I just modeled an I/O buffer and trying to validate my model using
HSPICE.

Brief setup of IBIS model :

1) [Ramp] was done with 50 ohm to VSS for rising;  50 ohm to VDD for falling
ramp.

2) I added four waveform tables since four are needed to dequately describe
a
   CMOS buffer as follows :

   a) [Rising Waveform]  with 50-ohm to VSS = 0.0V
   b) [Falling Waveform] with 50-ohm to VSS = 0.0V
   c) [Rising Waveform]  with 50-ohm to VDD = 3.3V +/- 10%
   d) [Falling Waveform] with 50-ohm to VDD = 3.3V +/- 10%


After model was complete, I ran a validation simulation using HSPICE with
the model instantiated as follows :

______________________________________________________________________
B_IO  nd_pu  nd_pd  nd_out nd_in nd_en v_out_of_in  nd_pc  nd_gc
+ file  = '../ibis_models/zspcixio_raw.ibs'
+ model = 'ZSPCIXIO'
+ typ   = 'typ'        $ choose typ = [typ/min/max]
+ buffer= input_output
+ power = on           $ [on] connects nd_pu/nd_pd/nd_pc/nd_gc to power
sources in ibis.
+ interpol = 2         $ 1=linear interpolation, 2=quadratic bi-spline
interpolation.
+ ramp_rwf = 2         $ Rising:  0-use ramp, 1-use 1st waveform data, 2=use
two waveforms
+ ramp_fwf = 2         $ Falling: 0-use ramp, 1-use 1st waveform data, 2=use
two waveform
+ nowarn
_________________________________________________________________________


Attached is brief model (with tables removed) and two validation waveforms.

Question :

1) First validation plot below has R_fixture = 50, V_fixture = 0.0 to match
my 1st
   [Rising Waveform].  Red line is Spice / Cyan color is IBIS model.

   I don't understand why the IBIS waveform has rail-to-rail levels
(0.0-3.3V).
   Spice makes sense because my V_fixture = 0.0, and this would decrease the
   high level.   It looks like IBIS runs the combination of all four
waveform
   tables and looks at initial & final voltage values and uses full logic
swings.

   Or : It could be my Voltage Range telling IBIS to always use these full
logic
        swings, so perhaps it's correct ??

    [Voltage Range]           3.3000V           2.9700V             3.6300V


2) 2nd validation plot has 100-ohm to Vdd/2 = 1.65V.  I did that to get
wider logic
   on Spice output (red line).  Now the levels are closer but slews are
still off.


Please let me know if there is a proper procedure to do this validation,
i.e. :

Given what I modeled above for the four V-t tables in IBIS with 50-ohm to
VDD/VSS,
what is a fair hookup to validate this model in Spice with matching slew
rates ?

Thanks
Doran David


|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email majordomo@eda.org
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to ibis-request@eda.org.
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993