Radovan, I suspect the reason people are asking for this data is because at the speeds we're dealing with, large packages are really acting like transmission lines. We can clearly see the effects in the lab - measure the input pin of a large device where the driver is serially terminated and you'll see the "ledging" characteristic associated with a transmission line. Lumped RLC parasitics, whether in per-pin or matrix form, won't necessarily reproduce this behavior. I use the term "necessarily" on purpose - some simulators convert package RLC parasitics into their transmission line equivalents - so you'll see transmission line behavior in all cases - but that is implementation-dependent. Explicitly expressing the parasitics as a transmission line should force the simulator to model it that way [or so one would hope]. This isn't an issue for all devices - but it's an issue for devices that are, say, more than 1" square with signaling edge rates less than 250ps. You can take the same rules of thumb for evaluating line length vs. edge rate and distributed/lumped line behavior at the board level and apply them to packages - the problem is the same. Fork/endfork statements are used to describe branches in package routing. Not that common anymore, I grant you - but once upon a time, plating bars and associated package stubs were common, and the fork/endfork statements were used to describe the stub. They're also common in the few cases where discrete devices are part of the package routing. Todd. Todd Westerhoff High Speed Design Group Manager Cisco Systems 1414 Massachusetts Ave - Boxboro, MA - 01719 email:twesterh@cisco.com ph: 978-936-2149 ============================================ "Always do right. This will gratify some people and astonish the rest." - Mark Twain ________________________________ From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Radovan.Vuletic@infineon.com Sent: Tuesday, October 18, 2005 2:42 AM To: tom@teraspeed.com; ray.anderson@xilinx.com; ibis-users@eda.org Subject: RE: [IBIS-Users] Per-Pin Distributed RLC Support Hi, Tom, I think that you put the right question, so let me elaborate this little bit further: 1. are there any available tools that generate/extract such RLC data out of package data? 2. before I submit the request to package experts to extract one more package format (they will crucify me anyway :-) I would like to know how many people would like/intend to use it 3. I know that the next question is not fair and that I compare here apples and oranges, but if you have one one side such RLC data and on the other side Sparse Matrix data what would you prefer to use? - My choice will be always Sparse Matrix - unless there is some very specific request 4. last but not least, quiet honestly, for me it is still little bit unclear what is meant to describe with "fork" and "endfork" branches ... Is it meant to indicate that for example 2 or more pads are sharing the same pin/ball or something similar - or I am missing the point totally? I thing that one picture (perhaps also in specs) could help on this place. Regards, Radovan -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Tom Dagostino Sent: Tuesday, October 18, 2005 2:39 AM To: Ray Anderson; ibis-users@eda.org Subject: RE: [IBIS-Users] Per-Pin Distributed RLC Support Ray Do any of the simulators support this? Tom Dagostino Teraspeed(R) Labs 13610 SW Harness Lane Beaverton, OR 97008 503-430-1065 tom@teraspeed.com www.teraspeed.com Teraspeed Consulting Group LLC 121 North River Drive Narragansett, RI 02882 401-284-1827 -----Original Message----- From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of Ray Anderson Sent: Monday, October 17, 2005 4:14 PM To: ibis-users@eda.org Cc: Ray Anderson Subject: [IBIS-Users] Per-Pin Distributed RLC Support In reviewing a large sampling of IBIS models from numerous vendors I have yet to find any that implement the distributed RLC format as described in the [Pin Numbers] section of the IBIS spec. (pages 117-120 in the 4.1 spec) I was wondering if anyone is aware of any published models that take advantage of this method of describing package parasitics. Regards, -Ray Raymond Anderson Senior Signal Integrity Staff Engineer Product Technology Department Advanced Package R&D Xilinx Inc. |------------------------------------------------------------------ |For help or to subscribe/unsubscribe, email majordomo@eda.org |with just the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or email a written request to ibis-request@eda.org. | |IBIS reflector archives exist under: | | http://www.eda.org/pub/ibis/email_archive/ Recent | http://www.eda.org/pub/ibis/users_archive/ Recent | http://www.eda.org/pub/ibis/email/ E-mail since 1993Received on Tue Oct 18 06:13:58 2005
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