RE: [IBIS-Users] functional check

Fabio,

Attached is a suite of ".MEAS" / ".PRINT" Spice directives, which we've
just started using here at Xilinx, in order to automate the validation
of our IBIS models against their Spice counterparts.

In the attached, "rnr_pad" is the Spice model output node, while
"nd1_out" is the IBIS model output node.

I hope that's helpful.

Regards,
-David Banas

--- Attachment begins here. ---

************************************************************************
*******
** Automated Measurements
************************************************************************
*******

* An arbitrary threshold of max/2 is used to "bootstrap" the
measurements.

.MEASURE TRAN max_sp MAX v(rnr_pad)
+ FROM = "5ns"
+ TO   = "5ns + clk_period"

.MEASURE TRAN half_max PARAM="(max_sp/2)"


* Measure the delays in the first rising edges of IBIS and Spice
waveforms.
* This tells us where to take our "high" and "low" averages.

.MEASURE TRAN dly_sp
+ TRIG AT=5ns
+ TARG v(rnr_pad) VAL=half_max TD=TRIG RISE=1

.MEASURE TRAN dly_ib
+ TRIG AT=5ns
+ TARG v(nd1_out) VAL=half_max TD=TRIG RISE=1


* Now, find the average "high" and "low" values, which will be compared,
* and used to calculate the "20%", "50%", and "80%" points that are used
* in subsequent measurements.

.MEASURE TRAN high_sp AVG v(rnr_pad)
+ FROM = "5ns + dly_sp + (clk_period/6)"      $ Using the middle third
to
+ TO   = "5ns + dly_sp + (2*clk_period/6)"    $ calculate the high
level.

.MEASURE TRAN high_ib AVG v(nd1_out)
+ FROM = "5ns + dly_ib + (clk_period/6)"
+ TO   = "5ns + dly_ib + (2*clk_period/6)"

.MEASURE TRAN low_sp AVG v(rnr_pad)
+ FROM = "5ns + dly_sp + (clk_period/2) + (clk_period/6)"
+ TO   = "5ns + dly_sp + (clk_period/2) + (2*clk_period/6)"

.MEASURE TRAN low_ib AVG v(nd1_out)
+ FROM = "5ns + dly_ib + (clk_period/2) + (clk_period/6)"
+ TO   = "5ns + dly_ib + (clk_period/2) + (2*clk_period/6)"


* Calculate 20/50/80 points.

.MEASURE TRAN eighty_sp
+ PARAM="low_sp + (high_sp-low_sp)*0.8"

.MEASURE TRAN eighty_ib
+ PARAM="low_ib + (high_ib-low_ib)*0.8"

.MEASURE TRAN fifty_sp
+ PARAM="low_sp + (high_sp-low_sp)*0.5"

.MEASURE TRAN fifty_ib
+ PARAM="low_ib + (high_ib-low_ib)*0.5"

.MEASURE TRAN twenty_sp
+ PARAM="low_sp + (high_sp-low_sp)*0.2"

.MEASURE TRAN twenty_ib
+ PARAM="low_ib + (high_ib-low_ib)*0.2"


* Measure rise/fall times.

.MEASURE TRAN tr_spice
+ TRIG v(rnr_pad) VAL=twenty_sp TD=5n RISE=1
+ TARG v(rnr_pad) VAL=eighty_sp TD=TRIG RISE=1

.MEASURE TRAN tr_ibis
+ TRIG v(nd1_out) VAL=twenty_ib TD=5n RISE=1
+ TARG v(nd1_out) VAL=eighty_ib TD=TRIG RISE=1

.MEASURE TRAN tf_spice
+ TRIG v(rnr_pad) VAL=eighty_sp TD=5n FALL=1
+ TARG v(rnr_pad) VAL=twenty_sp TD=TRIG FALL=1

.MEASURE TRAN tf_ibis
+ TRIG v(nd1_out) VAL=eighty_ib TD=5n FALL=1
+ TARG v(nd1_out) VAL=twenty_ib TD=TRIG FALL=1


* Measure duty cycles.

.MEASURE TRAN th_spice
+ TRIG v(rnr_pad) VAL=fifty_sp TD=5n RISE=1
+ TARG v(rnr_pad) VAL=fifty_sp TD=TRIG FALL=1

.MEASURE TRAN th_ibis
+ TRIG v(nd1_out) VAL=fifty_ib TD=5n RISE=1
+ TARG v(nd1_out) VAL=fifty_ib TD=TRIG FALL=1

.MEASURE TRAN tl_spice
+ TRIG v(rnr_pad) VAL=fifty_sp TD=5n FALL=1
+ TARG v(rnr_pad) VAL=fifty_sp TD=TRIG RISE=1

.MEASURE TRAN tl_ibis
+ TRIG v(nd1_out) VAL=fifty_ib TD=5n FALL=1
+ TARG v(nd1_out) VAL=fifty_ib TD=TRIG RISE=1

.MEASURE dc_spice
+ PARAM='th_spice/(th_spice + tl_spice)'

.MEASURE dc_ibis
+ PARAM='th_ibis/(th_ibis + tl_ibis)'


* Measure the errors.

.MEASURE TRAN high_err
+ PARAM="(high_ib - high_sp)/high_sp"

.MEASURE TRAN low_err
+ PARAM="(low_ib - low_sp)/low_sp"

.MEASURE TRAN risetime_err
+ PARAM="(tr_ibis - tr_spice)/tr_spice"

.MEASURE TRAN falltime_err
+ PARAM="(tf_ibis - tf_spice)/tf_spice"

.MEASURE TRAN dutycycle_err
+ PARAM="(dc_ibis - dc_spice)/dc_spice"


*** Report the results.

.PRINT high_err
.PRINT low_err
.PRINT risetime_err
.PRINT falltime_err
.PRINT dutycycle_err

--- Attachment ends here. ---


> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf
> Of Fabio BRINA
> Sent: Wednesday, November 08, 2006 7:47 AM
> To: ibis-users@eda.org; ibis-info@eda.org
> Subject: [IBIS-Users] functional check
> 
> 
> Hello experts,
> 
> do you know were I can find some documentation
> about the matching between IBIS model simulation
> and Spice / Eldo simulation?  (Functional Check).
>  I'd like to understand (for example)  in
> witch way the EDA tool define the voltage
> controlled current sources (of the ibis representation)
> frome ibis model.
> 
> Thank you,
> Fabio
> 
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