Date: Thu Jan 11 2007 - 08:08:19 PST
Hello everybody I 'd like to have some information about a strange behaviour of Open drain buffer Ibis model. I have noticed a mismatch between Transistor level and Ibis model voltage output during a transient analysis, considering the same buffer. In fact in presence of the same input voltage wave and for a high value of load resistance(for example 20Kohm)connected to power, we can observe a delay between TL output and Ibis output. In the Ibis file, for Open drain, Rise and fall waves tables have been extracted considering the same resistance connected to Power (20Kohm). What is the cause of this strange behaviour? Thanks and best regards Roberto Izzi -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993
