Hi, If Timing Measurement Conditions describing parameters (Vmeas Rref Vref Cref ) are included in a model, Does this imply that the delay ( core i/p to pad ) of IBIS or SPICE Buffer with this load conditions and measured at Vmeas will be same. Tdelay (Vmeas Rref Vref Cref ) (IBIS) = Tdelay (Vmeas Rref Vref Cref ) (SPICE/Lab measurement) Tdelay <= Delay from input to Pad With regards, Muniswara Reddy . V Design engineer, PIPD-IO group, Bangalore. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Sat Apr 12 01:06:23 2008
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