RE: [IBIS-Users] question about IBIS simulation for a complete inverter

Ji

Historically IBIS Signal Integrity simulators are not designed to simulate
the transfer function of the parts in the nets you are simulating, they only
concern themselves with the interaction of the I/O buffers and the
transmission line medium that is between them. There is no description of
the logic function, delay or any of the other requirements that may be
needed to generate the timing of signals from input to output in an IBIS
model. There are some timing simulators that do at least some level of
input to output simulation.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065

503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of ji xiao
Sent: Wednesday, March 17, 2010 8:06 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] question about IBIS simulation for a complete inverter

Dear Sir/Madam,

As a beginner worked with IBIS model, I met a problem about the IBIS
simulation for a complete device. Let's take an inverter as an example. If I
want to model a complete inverter including the transfer function by using
IBIS, do I just need to simulate the output model only(i.e. does the output
model contain the transfer function) ? or cascade IBIS input model with
output model?
If we need to cascade them, does that mean just to receive the output signal
of the input model as the input signal of the output model?
 
Thanks and regards,
Ji Yuancheng

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