Date: Fri Aug 05 2011 - 01:15:44 PDT
Hello anand,
i would check the waveform first.
it looks very suspicious.
( 30ns with 10 timepoints )
may be you could throw it away and use the ramp only
regards
Eckhard
Mit freundlichen Grüßen / Best regards / Cordiali saluti / ystävällisin terveisin
Eckhard Lenski
Nokia Siemens Networks GmbH & Co. KG
NWS EP CP HW CAD libraries
St.-Martinstr. 76
80240 München
Germany
phone : +49 89 5159 17080
email: eckhard.lenski@nsn.com
http://www.nokiasiemensnetworks.com/ibis
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________________________________
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of ext Graham Kus
Sent: Friday, August 05, 2011 12:56 AM
To: Anand Ramalingam; IBIS
Subject: RE: [IBIS-Users] simulating ringing behavior
Anand,
We incorporate a bandgap generator as part of our LVDS IBIS model. The S2I file points to a Spice deck that incorporates the bandgap generator as part of an extracted netlist from the SoC IP block. It's not exactly human readable and takes longer to converge, but it seems to work.
-Graham
From: Anand Ramalingam [mailto:anandr@Magma-DA.COM]
Sent: Thursday, August 04, 2011 6:53 PM
To: Graham Kus; IBIS
Subject: RE: [IBIS-Users] simulating ringing behavior
Thanks Graham for your inputs.
I am using the same load circuit on both the spice as well as ibis simulator.
As you have correctly deduced, I have set up the ibis file to extract the output buffer structure. How do I incorporate the band gap generator in the ibis extraction. Any pointers would be helpful.
Thanks
Anand
From: Graham Kus [mailto:Graham.Kus@conexant.com]
Sent: Thursday, August 04, 2011 5:46 PM
To: Anand Ramalingam; IBIS
Subject: RE: [IBIS-Users] simulating ringing behavior
Hi Anand,
Are you using the same load circuit in Spice as in the IBIS simulator? For example, if you're using an RLC component terminator in Spice then it pays to use the same RLC circuit in IBIS simulator (as opposed to a transmission line).
Another suggestion would be: perhaps your S2I file is only setup to model the output buffer structure (typically the case). It seems that you are incorporating a bandgap generator in the Spice deck to reach 2.6V low logic voltage, so its contribution to the ripple would be modeled in Spice but obviously ignored by an IBIS extraction of an output buffer structure.
-Graham
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Anand Ramalingam
Sent: Thursday, August 04, 2011 6:29 PM
To: IBIS
Subject: [IBIS-Users] simulating ringing behavior
I want to simulate the ringing behavior found in following signal in IBIS. This snapshot is from the spice simulation.
(logic high - 3.3v ; logic low - ringing between 2.65 - 2.75v)
The ibis simulation yields the following waveform
The logic low's ringing is not captured in IBIS.
I tried changing the numerical algorithm from TRAP to GEAR in spice simulation to make sure it is not a numerical artifact. The following are the rising and falling tables
|
[Rising Waveform]
R_fixture = 50
V_fixture = 3.3
|
| Time V(typ) V(min) V(max)
|
0 2.72122 NA NA
8.3554p 2.72933 NA NA
66.4303p 3.0285 NA NA
0.109129n 3.15831 NA NA
0.130693n 3.19638 NA NA
0.160088n 3.23045 NA NA
0.204145n 3.25956 NA NA
0.263155n 3.27863 NA NA
0.494298n 3.29621 NA NA
31.25n 3.29998 NA NA
|
[Falling Waveform]
R_fixture = 50
V_fixture = 3.3
|
| Time V(typ) V(min) V(max)
|
0 3.30001 NA NA
77.4596p 3.2744 NA NA
0.142103n 2.91665 NA NA
0.446801n 2.67684 NA NA
29.4488n 2.65867 NA NA
29.9943n 2.76514 NA NA
30.1222n 2.65842 NA NA
30.668n 2.76505 NA NA
30.7944n 2.65829 NA NA
31.25n 2.76182 NA NA
|
As one can see in the Falling table the waveform cycles between 2.65 and 2.76 but it does not get reflected when the file is simulated.
Any pointers in getting ringing behavior on the ibis simulation would be helpful.
Is there any setting in the spice file that needs to set? I am using the following:
+ typ=typ
+ ramp_fwf =1
+ ramp_rwf =1
Thanks
Anand
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