RE: [IBIS-Users] Fwd: FW: ddr103_v.scs true differential buffer IBIS modelling

From: Muranyi, Arpad <Arpad_Muranyi@mentor.com>
Date: Wed Oct 15 2014 - 10:32:46 PDT
Shivani,

It is not unusual to see “no” current between the P and N
pins of a differential buffer.  It all depends on how the
internal circuit of the buffer is designed.

Thanks,

Arpad
==========================================================

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Shivani Sharma
Sent: Wednesday, October 15, 2014 12:19 PM
To: ibis-users@eda.org
Subject: [IBIS-Users] Fwd: FW: ddr103_v.scs true differential buffer IBIS modelling

Hi all

I am trying to model true differential buffer  following the “Series model approach” at  http://www.vhdl.org/ibis/summits/oct03/muranyi.pdf. ).
I am assuming that a differential buffer should have some sort of differential current that would flow from PADP to PADN when the two nodes are at different voltages.

I am trying to sweep PADP and PADN voltages to see current between the two PADS. However. the currents I see are in nano-Amps indicating that there is almost no differential current. Current into PADN is almost independent of DC-voltage forced on PADP. Is this an expected behavior or am I missing something in this activity?

DC sweep is applied on padn and padp is kept at different voltages (-1.2 to 2.4 in steps of 0.4V) .

Regards
Shivani




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Received on Wed Oct 15 10:33:22 2014

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