All: Correction: The Summit is on FRIDAY, November 14, 2014. Bob All: Attached is the tentative Agenda for a full meeting with 11 presentations. We look forward to seeing you in Shanghai. Registration information is at the end. Lance and Bob ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: 8:15 - 17:30, Tuesday November 14, 2014 Location: Parkyard Hotel Shanghai 699 Bibo Road Zhangjiang Hi-Tech Park Shanghai 201203 P.R. China Rooms: Ballroom ABC (Look for signs) Sponsors: Huawei Technologies (Primary) ANSYS Intel Corporation IO Methodology Keysight Technologies Synopsys Teledyne LeCroy ZTE Corporation ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:15 SIGN IN - Vendor Tables Open at 8:30 8:45 Welcome - Li, JinJun (Huawei Technologies, China) - Mirmak, Michael (Chair IBIS Open Forum) (Intel Corporation, USA) 9:00 Activities and Direction of IBIS Mirmak, Michael (Intel Corporation, USA) 9:25 Handling of Overclocking Caused by Delay in Waveform Tables Biernacki, Radek*; Yan, Ming*; Wolff, Randy**; Butterfield, Justin** (*Keysight Technologies, **Micron Technology, USA) 9:55 An Effective Solution to Simulate Composite Current When Over-clocking Chen, XueFeng (Synopsys, China) 10:25 BREAK (Refreshments and Vendor Tables) 10:45 True Differential IBIS Model for SerDes Analog Buffer Sharma, Shivani; Malik, Tushar; Kukal, Taranjit (Cadence Design Systems, India) 11:20 Best Practices for High-Speed Serial Link Simulation Hou, MingGang (ANSYS, China) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) - Vendor Tables 13:30 Connector Via Footprint Optimization for 25Gbps Channel Design Dai, WenLiang; Su, ZhouXiang (Xpeedic Technology, China) 14:00 Using IBIS-AMI Model for 25Gbps Retimer Simulation Wei, MaoXian; Yin, ChangGang; Zhu, ShunLin (ZTE Corporation, China) 14:30 IBIS AMI Validation Mahmod, Zilwan; Ekholm, Anders (Ericsson, Sweden) 15:00 BREAK (Refreshments and Vendor Tables) 15:20 Signing IBIS Model Against DDR4 Spec Malik, Tushar; Kukal, Taranjit (Cadence Design Systems, India) 15:55 Corner Considerations Ross, Bob (Teraspeed Labs, USA) 16:30 Ad Hoc Presentations and Discussion Skew Effect Analysis Using IBIS-AMI Model Dong, XiaoQing (Huawei Technologies, China) 17:20 CONCLUDING ITEMS 17:30 END OF IBIS SUMMIT MEETING ------------------------------------------------------------------ To Register by November 11, 2014: Name: E-mail address: Company: Top-level Web Link: Country: Send to BOTH: Lance Wang, IO Methodology Inc. lwang@iometh.com Bob Ross, Teraspeed Labs bob@teraspeedlabs.com -- Bob Ross Teraspeed Labs http://www.teraspeedlabs.com bob@teraspeedlabs.com Direct: 503-246-8048 Office: 971-279-5325 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail mikelabonte@eda-stds.org |or ibis-request@eda-stds.org | |IBIS reflector archives exist under: | | http://www.eda-stds.org/ibis/email_archive/ Recent | http://www.eda-stds.org/ibis/users_archive/ Recent | http://www.eda-stds.org/ibis/email/ E-mail since 1993Received on Thu Nov 6 14:09:53 2014
This archive was generated by hypermail 2.1.8 : Thu Nov 06 2014 - 14:10:00 PST