Greetings IBIS Gentle folk --
I would like to respond to a couple of Bob Ross's comments on Version 1.0
of the specification.
1. In regards to the package and pin model, I believe the IBIS spec
assumed the model shown below:
DIE-----/\/\/-----CCCCC-------PIN
(R) (L) |
|
--- (C)
---
|
|
GND
However, I think the suggestion of removing the series R and
distributing the capacitance is right on the mark. It should
allow IBIS to handle large ceramic PGA packages (A.K.A.
miniature helecoptor landing pads) where the bondwire/leadframes
are long enough to be considered transmission lines. My only
question is, what exactly is C_pkg and how is it measured (is
it a calculated value based on the Zo of the wire)? Please reply.
2. In regards to the specified voltage ranges: The reason that the
ranges are (apparently) so extreme is to take into account the
effects of driving an unterminated transmission line. Remember
that when an incident voltage wave hits the end of an unterminated
line it will reflect back to the source at double the amplitude.
Thus, the power clamp diode on a CMOS (0 to 5v) output could have to
clamp a 10v reflection. (Likewise, the gnd clamp diode must be
able to handle a -5v reflection). That is the reason for specifying
a range of POWER + POWER for the power_clamp and GND - POWER for
the grd_clamp. I agree that most everyone is going to extrapolate
the clamp diode curves to those ranges when they fill in the table.
The effort in the spec was, I believe, to make sure that sufficient
data was included (i.e. make sure it went well beyond the knee of
the diode curve).
Best Regards,
Stephen Peters
Intel Corp.
Received on Fri Aug 27 17:16:59 1993
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