Hello IBIS folks,
I just want to clarify a few things regarding the packaging circuit
and other items mentioned in the recent EMAILs.
In regards to the package and pin model, the IBIS spec assumed the
following circuit:
R L
DIE---------RRRRR-----LLLLL-------PIN
| |
| |
=== C_comp === C_pkg
| |
| |
GND GND
C_comp represents the parasitic capacitance of the output transistors.
It is used because the V/I curve based behavioral output structure
does not represent any capacitances. Therefore, C_comp can not be
omitted.
The RLC circuit represents the Ohmic resistance, inductance and
capacitance of the bond wire and pin. If you like, you can view it
as a lossy transmission line, modeled in a single lump. (The U-lines
in HSPICE are done the same way, except one can control the number of
lumps with the WLUMP and MAXL parameters). Since the length of the
bond wire and pins are relatively short in a normal package, I
thought we did not need to complicate matters unnecessarily by
distributing the values over many lumps. However, just because IBIS
gives the single lumped values, it does not mean that a simulation
tool vendor could not distribute them, as HyperLinx did it "from day
1", or model it as a lossy transmission line. Even though its effect
is small, I would NOT remove the series resistor, because it is part
of the lossyness of the lossy transmission line.
Even though I personally have not done these measurements, I know that
we (Intel) measure these values (L and C) with an HP 4192 L/F impedance
analyzer.
Another way to obtain these values is with the IPA310 system
(Interconnect Parameter Analyzer) developed by Tectronix recently.
That equipment will give you these values directly, but it is also
capable of much, much more.
Regarding Bob's suggestion about combining R_pkg into
pull up and pull down:
"I can accept Kellee Crisafulli's justification on R_pkg for future
MCM macomodeling capability. But an alternative might be to include
the R characteristics in the PULLUP and PULLDOWN data."
I do not believe in combining things like that. Package and die
modeling should be kept separate (i.e. stay modular) so that if a new
revision occurs in one area, e.g. package, it should be easy to
change things whithout effecting the other area. Besides, many
vendors do it this way already, why should we be different.
Voltage ranges, clamping diodes:
--------------------------------
Steven Peters is right about explaining the extreme voltage ranges.
Simulators usually do not simulate part break down, I mean burn up.
Just because a real part might blow up by being continuously forward
biased around 2-3 volts, it does not mean that they can not handle
short 2-3 V spikes. Since reflections may result in such or even
greater voltages, we must define the diodes beyond that range to get
the realistic clamping effects. You must also remember that these
clamping effects can also be considered as the diode being a driver
trying to pull back the signal to where it should be. This "driven
clamping edge" goes back down the line as a signal, and can not be
ignored.
As a bad example, NOT TO BE FOLLOWED, let me bring it up here that
I have seen some silicon models where they characterized the device
only between -0.6 and Vcc+0.6 volts in such a way that the clamping
currents were tens of kilo-Amps (10*10^3 Amps) at about 0.8 - 0.9
volts already when I did a DC sweep on it! This is essencially a
perfect clipping, but as I said before, this "clipping edge" goes
back down the line as a signal too.
Therefore, I believe the best solution is if we define the V/I curve,
even if we need to extrapolate it. It is true that simulators can do
the extrapolations easily, but they don't all do it. In HSPICE (and
maybe other SPICE flavors also) if you define the diode up to let's
say 500 mA @ -2 V (using a PWL current source), it will give you 500
mA at all voltages below -2 V.
To answer Bob's question:
"In section 2) of "NOTES ON DATA DERIVATION METHOD" at the end, no
explaination is given why the voltage ranges for the GND_CLAMP and
POWER_CLAMP are different",
I must say that they were originally the same. They used to be:
-POWER to GND for the ground clamp and VCC to VCC+POWER for the vcc
clamp. We (IBIS folks) changed this in the meetings to be what it is
now, so that the 3-stated leakage currents could be also included
some way. Therefore the range between the GND and POWER voltage can
be used for this purpose on the ground clamp.
To answer Bob's 2nd comment:
"Regarding Steven Peter's comments on the reason for the voltage
ranges, the extension of the GND_CLAMP model to POWER in the REVERSED
BIASED direction makes sense with repect to handling a reflected
wave. However, the POWER_CLAMP range should extend to GND (Rather
than just to POWER) for the same reason in the REVERSED BIASED
direction. The only reason I can think of for not extending the
POWER_CLAMP is that it's characteristics can be concatenated with the
GND_CLAMP characteristics to form an INPUT model (or model for I/O or
3-STATE in the input mode)".
Well, the ground clamp is NOT going to do much with reflected waves in
its reverse biased region. When the device in not 3-stated, the
pulldown transistor, or the pull up transistor is a lot more active
in that region, so they will handle all the reflections without the
help of a few uA of lekage current from the diode. When they are
3-stated, a few uA of lekage current is going to look like an open to
the reflections. So the real reason to have that additional range
there for the ground clamp is to be able to model a 3-stated
situation (mostly to find a DC operating point).
Bob's statement about:
"In the FORWARD BIASED clamping direction in a transmission line
environment, the algorithm may see initially the full voltage signal,
but would eventually converge to a much lower value based on the
non-linear VI clamping characteristics in conjunction with the
characteristic impedance of the line. If, for example, there is a -5
Volt reflected step signal in a 50 Ohm line, the maximum current seen
at the termination end of a GND_CLAMP cannot initially exceed 100
milliAmps, thus eventually causing the convergence to a voltage value
at much less than 5 Volts at the clamping end. Since the -5 Volt
signal comes from undershoot, it would not normally provide a buildup
of voltage across the clamp over several reflection intervals."
Yes, BUT if one has a 10 Ohm line and a week clamping diode, which
can give you about 0.5 Amps at -5 volts, then the undershoot will be
-5 V, if we calculate as Bob did. Therefore it is better to be safe
than sorry, and define the diodes to -5 V (or make sure that all
simulators on the world extrapolate the way they should).
Regarding the Vtable DEFINITION comments of Bob:
------------------------------------------------
When I designed the behavioral models on HSPICE, I approached this
issue from an arbitrary, but somewhat more theoretical viewpoint. I
decided to be in the positive voltage range for the active part of
the V/I curves and in the negative range for the "clamping" part of
the V/I curves. (To clarify myself, by the active region I mean the
0 to 5 volt range of the pull down, and the 5 to 0 volt range for the
pull up transistors, these numbers with respect to GND now). Thus as
the voltage becomes more and more positive across the transistor, the
transistor turns on more and more. This provides a nice symmetry, in
my opinion.
What does this have to do with "offset from Vcc"? The Vcc-relative
approach is not done with the purpose of being in the same offset
direction from the Vcc pin.
Since Bob's recommendation would just simply turn the polarity around
for the voltages in the pull up table, it really does not matter to
me whether they are positive or not in the above mentioned active
range. Is that really that much easier to read and understand? Does
that really give more value to IBIS? If all of our IBIS fellows
agree, I don't mind to change it...
Don Telian strongly wants to keep it as it is, though, since we
already distributed hundresds of models this way.
Regarding dV/dt:
----------------
To answer Bob's question:
"For consistency and extrapolation purposes, should the 'min' and
'max' entries of the RAMP dV/dt_r and dV/dt_f also be associated with
VOLTAGE RANGE 'min' and 'max' values?"
YES, this is outlined in IBIS 1.0 towards the end:
--------------------------------------------------------------------------------
| 6. Typ, Min, and Max must all be posted, and are derived at the |
| same extremes as the V/I curves, which are: |
| |
| Ramp times for CMOS devices: |
| typ = nominal voltage, 50 degrees C, typical process |
| min = low voltage tol, 100 degrees C, typical process, minus "Y%" |
| max = hi voltage tol, 0 degrees C, typical process, plus "Y%" |
--------------------------------------------------------------------------------
Sincerely
Arpad Muranyi
Intel, Coprporation
Received on Wed Sep 1 17:40:12 1993
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