3-D model topics

Hi Siuki, and all others,

Sorry for the delay in responding to your comments on the 3-D model,
but here is the way I see it.

>> If we want to characterize the switching characteristics of the
>> transistor while it is being turned on (i.e. while its gate voltage
>> is transitioning from 0V to 5V), we would have to take a family of
>> V/I curves at various gate voltages. There is nothing new in this
>> idea, most transistor data books publish such family of curves for
>> both FETs and BJTs. Our problem is that it is very difficult or
>> impossible to access the voltage waveform on the gate of an output
>> transistor.

> Is the difficulty with actual physical measurement such that you cannot
> probe the input node of the gate? Then how about in spice simulation? I
> can thinks of a method like this: use the Vds/Ids/Vgs family of curves
> and Vgs/Time of the input voltage. Mapping Vgs from the curve 1 to Vgs
> in curve 2, then you can arrive at a Vds/Ids/Time surface.

> Mathematically, curve 1 is Ids = f(Vds, Vgs)
> curve 2 is Vgs = g(time)
> combining both, Ids = f(Vds, g(time))

You can do this only on SPICE, but not with real devices...

> In physical measurement, curve 1 can be obtained by slowly sweep I/V curve
> of the output by setting input voltage to a set of fixed values. The only
> limitation is: you cannot isolate either the pull-up or pull-down. In IBIS
> [pull-up] and [pull-down] voltage specifications are different. Curve 2
> can be obtain by probing the input node voltage get a waveform by an
> oscilloscope.

This "only limitation" you mentioned in actually not the only one.
Think of an ASIC, for example. You do not have access to buffer
inputs in an ASIC or a more complex device to slowly sweep its input.

Even if you did, I do not believe that slowly sweeping an input is
going to slowly switch the output as well, due to the gain in the
pre-driver section. In my opinion, this approach would not work.

Anyways, the purpose is not to derive a way to find out what the
waveform is on the gate (or base) of the output transistor. (I could
not care less about that). It is to see the current / voltage / time
relationships on the output of the buffer. For that, we can treat the
buffer itself as a black box and forget about the waveforem on the
gate or base.

>> The nice part of this approach is that the device under test does not
>> have to be a MOSFET transistor. In fact, it can be anything and we
>> can treat it as a black box. The surface plot will still fully
>> describe its characteristics.
>
> I think this may not be as device independent as first appear. In the
> analysis, the MOS is working in a common-source mode. Source current
> is a function of (gate-source, drain-source) so that change of drain
> voltage only affect one variable: the drain-source voltage. In
> common-emmiter mode, as in ECL output stage, collector current is a
> function of (base-emitter, collector-emitter) so change of emitter
> voltage affect both variables.

Without having done too much research on this, I think it actually is
device independent. (It needs to be confirmed, though). What you are
saying is true if you relate things to the gate voltage waveform. But
if you treat the device as a black box, and only look at the current /
voltage / time relationship on the output pin, you are actually
characterizing the impedance of the buffer at any given time while it
is switching and thereafter, regardless whether it is a BJT, MOSFET,
open collector, emitter follower, etc... Since this impedance is a
function of time and voltage of the output pin, but the voltage is
actually a function of the loading impedance and the output current,
we can also say that the driver impedance is also a function of the
load impedance.

>> The only difficult part is that we must have a current meter that is
>> extremely fast. There could be several hundred milliamp changes in a
>> couple of nanoseconds. Such current changes are very susceptible to
>> parasitic inductances, therefore a careful measurement methodology
>> must be worked out to obtain correct data.

> This will be a concern for company which does not the kind resources
> Intel has. Further more, mixing DC and AC parameters in your calculation
> means you have to take into account all reactive elements and high
> frequency effects.

That is why I feel that a good measurement methodology must be worked
out by which I also mean that is should be relatively low cost, so
that people can afford it. And you are right this involves the
reactive elements (packaging also).

> I am confused about the purpose of the [RAMP] data in the ibis file. I
> think its purpose is to construct the waveform of the sending end before
> any reflection arrives. Does it mean that with the I/V/T characterization
> method, [RAMP] information is no longer required.

Yes, I/V/T would make the ramp stuff meaningless. The ramp times are
just kind of a rough description of the switching characteristics of
the buffer.

If there are any more comments, feel free to EMAIL. This is a new
territory for mee too, I would like to hear your reactions.

Sincerely
Arpad Muranyi
Intel, Coprporation
Received on Fri Oct 1 09:14:37 1993