Response to the Quad article from Arpad

Text item: Text_1

Hi IBIS folk,

This is my response to the article "Measuring Pull-down Currents in
CMOS devices" by Jon Powell and Chris Myles (JP&CM) at Quad Design.

1) Generally speaking, I must say that I couldn't agree more with
the theory presented in the article. I am fully aware of the fact
that the bulk currents are different in an ON and an OFF transistor,
as shown in Figures 2 and 3. I also agree with the equations on page
2 which state that the difference between the ON and OFF transistor's
drain current is equal to the ON transistor's source current if and
only if the bulk currents are equal and the OFF transistor's source
current is assumed to be zero.

          Id1-Id2 = -Is1, iff Ib1 = Ib2 and Is2 = 0

2) I also agree that the difference between the ON and OFF
transistor's bulk current can be plotted as shown in Figure 5 and if
combined with the curve shown in Figure 4, we arrive to the curve
shown in Figure 6.

3) The difference in our opinion came from the interpretation of the
IBIS specifications. I must admit that the specifications do not
clearly spell out how to deal with this issue. We must address this
problem so that the rev2 specification would be clear and unambiguous.

Here is how I approached the problem:

It was not my goal to provide transistor-theory correct Is curves in
the pulldown and pullup tables. I assumed that a simulator tool would
use the clamping curves as constantly present I-V curves, and it would
add the appropriate pullup or pulldown curve to it when the buffer was
turned on. This is the key assumption, which I believe nearly all of
us have made, that should be clearly documented in the IBIS
specifications.

With lab measurements we can only obtain I-V curves for 3-stated or
enabled buffers. A 3-stated buffer can be used to obtain the I-V
curves needed for the clamping tables, but an enabled buffer gives
the sum of the clamp and the transistor. This sum curve cannot be
added to the clamp, as stated above, because it already includes the
clamp currents. This is how I arrived at the "subtract method". In
order to be able to add the I-V curves in the clamp sections to the
I-V curves in the pullup and pulldown sections for an enabled buffer,
I had to provide the difference of the two for those tables. This is
what the JP&CM article calls Id1-Id2.

I did not have an easy way to subtract these curves from each other
in the early days. Knowing from theory that the source current of a
MOSFET transistor is fairly symmetric around the origin (just like
figure 6 shows it in the JP&CM article), first I generated models
based on the approximation that the difference of the two is the
positive part of the I-V curve flipped over. Therefore, in the early
models, I generated symmetric curves for the pulldown and pullup
tables, and used the 3-stated I-V curves as measured for the clamp
tables.

I used this method until I made myself a tool with which I could
subtract the 3-stated buffer's curve from the enabled buffer's curve.
I was very surprised by the non-monotonic curve I saw. First I
thought I had a bad silicon model; however, after investigating the
issue further, I came to the conclusion that the curves were correct
the way they looked. In the spirit of continuous improvements, I
started to make models with the "subtract method", which were
non-monotonic but were more accurate (assuming the curves are later
summed) than the previously described models generated with the
"symmetry method".

In the case of the non 3-statable buffers there is no way to measure
the clamping curves alone. Since a buffer always appears as the sum
of the transistor and the clamp, I decided to put all zeroes in the
clamp sections (i.e. omitted the clamp keywords) and lumped
everything into the pulldown and pullup I-V tables. Based on the
summing assumption (that must be documented) for the simulation
tools, I did not see anything wrong with this method.

You might wonder why it is necessary to subtract, when the tool adds
the curves up again. I could have provided the measured curves just
as they are. For one thing, I wanted to avoid the "double counting"
of the clamp curves. Another important reason was the Vcc
relativness of the pullups and the power clamps. However, it is
beyond the purpose of this writing to explain these issues in detail.

I believe that the method described above presented correct models and
I do not see any mathematical errors in the process. I was simply
using the available keywords to allow the most accurate simulations
possible.

4) For the sake of completeness, I need to point out that something
must be wrong (perhaps due to an typing error) with the equations on
page 3 of the JP&CM article, since the left hand side is equal to 0 as
shown.

Also, on page 5, it is stated that SPICE models assume a zero bulk
resistance and it would be more realistic to use bulk resistances in
the range of 100 Ohms. First of all, the two SPICE flavors I have
used so far do NOT assume that. There are three parameters which can
be used in the .MODEL section: Rd for drain, Rs for source, and Rb
for bulk resistances. (It is another story that sometimes these are
not defined in a model, in which case they default to zero). Second,
100 Ohms seems to be quite large, however if expressed in terms of
sheet resistance, 100 Ohms/square is certainly possible. Consider a
100 Ohm series (bulk) resistance with a clamping diode: at -5 V it
would allow about 50 mA only. Most devices draw a lot more than that
(if they survive the -5 V or their curve is extrapolated to -5 V).

Still referring to page 5, in my experience, we are not trying to
detect a 5 mA difference between two 1.0E+20 mA (1.0E+17 Amp) numbers.
Such currents occur usually when the drain, source and bulk
resistances are not defined in a transistor level SPICE model. If a
buffer is modeled correctly in SPICE (or if lab measurements are
used), these large currents are in the range of 5 to 15 Amps at -5
volts, but they can be as low as 7 mA at -3.5 Volts (in the case of
some DRAM modules I tested). A 30 to 40 mA difference WILL NOT cause
mathematical floating point errors between two 15 Amp numbers. Also,
we might neglect a 30 to 40 mA difference in the case of two 15 Amp
clamping currents, but we certainly cannot do that if the clamps are
weak, as in the case of DRAMs.

5) Regarding the suggestion that using realistic bulk currents will
result in monotonic curves, I found the followings from simulations:
The shape of the curve depends on the proportions between the
drain/source/channel resistance and the bulk resistance (and possibly
the channel resistance as well). When the bulk resistance is small,
most of the current goes through the bulk, resulting in a
non-monotonic curve for Id1 - Id2. When the bulk resistance is
relatively large, most of the current goes through the channel, and
the Id1 - Id2 curve becomes monotonic in shape. However, a lab
measurement on a 74HCT245 buffer showed that the difference between a
3-stated buffer curve and an enabled buffer curve (Id1 - Id2) was
indeed non-monotonic. This indicated to me that the bulk resistance
must have been relatively small with respect to the drain and source
resistances.

I hope this has provided some good background information. I will be
working in the future to enusre that the proper set of assumptions are
documented in the IBIS specifications. (Watch for a bird fly by). I
welcome your comments as we all labor together to make IBIS as clear
as possible.

Sincerely
Arpad Muranyi
Intel Corporation,
Folsom, CA
(916) 356-2558
Received on Tue Apr 26 09:32:30 1994