Hello IBIS members:
Thank you for your responses on BIRD6.1. BIRD6.1 shifts to BIRD6.2
toward my understanding of a common position. Refer first to the
ANY OTHER BACKGROUND INFORMATION section for change discussion.
More comments are welcome.
Changes:
clarifications in "vdiff" definition and description
"tskew" replaced by polarity sensitive "tdelay"
Analysis Path text and diagram revisions
Bob Ross, Interconnectix, Inc.
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Buffer Issue Resolution Document (BIRD)
BIRD ID#: 6.2
ISSUE TITLE: Differential Pin Specification
REQUESTOR: Bob Ross, Interconnectix, Inc.
DATE SUBMITTED: 12 January 1994
DATE REVISED: 29 January 1994, 5 February 1994
DATE ACCEPTED BY IBIS OPEN FORUM: {will be filled in when accepted}
******************************************************************************
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STATEMENT OF THE ISSUE:
Several components contain pins which operate in a differential mode with
respect to other pins. Since this operation in inherent to a component,
the IBIS document should be extended to specify this functionality.
******************************************************************************
STATEMENT OF THE RESOLVED SPECIFICATIONS:
An additional optional keyword, [Diff_Pin], is added to the specification.
|==========================================================================
| Keyword: [Diff_Pin]
| Required: Optional
|Description: Used to associate differential pins, their differential
| threshold voltages and differential timing delays.
| Sub-Params: inv_pin, vdiff, tdelay_typ, tdelay_min, tdelay_max
|Usage Rules: Entries follow these rules: Only differential pin pairs
| are entered. The [Diff_pin] column contains a non-inverting
| pin number and the inv_pin column always contains the
| corresponding inverting pin number for output and I/O output.
| The vdiff column contains the specified differential threshold
| voltage between pins if the pins are Input or I/O Model_types.
| For Output only differential pins, the vdiff entry is 0V.
| The tdelay columns contain launch delays of the non-inverting
| pins relative to the inverting pins. The values can be either
| polarity.
|Other Notes: The output pin polarity specification in the table overrides
| the [Model] Polarity specification such that the pin in the
| [Diff_pin] column will be Non-Inverting and the pin in the
| inv_pin column will be Inverting. This convention allows
| one [Model] to be used for both pins.
|
| Column length limits are:
| [Diff_Pin] 5 characters max
| inv_pin 5 characters max
| vdiff 9 characters max
| tdelay_typ 9 characters max
| tdelay_min 9 characters max
| tdelay_max 9 characters max
|
| Each line must contain either four or six columns. If "NA" is
| entered in the vdiff, tdelay_typ or tdelay_min columns, its
| entry will be interpreted as 0V or 0ns. If "NA" appears in
| the tdelay_max column, its value will be interpreted as the
| tdelay_typ value. When using six columns, the headers
| tdelay_min and tdelay_max must be listed. Entries for the
| tdelay_min column are based on minimum magnitudes; and
| tdelay_max column, maximum magnitudes. One entry of vdiff
| regardless of its polarity is used for difference magnitudes.
|---------------------------------------------------------------------------
[Diff_Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
|
3 4 150mV -1ns 0ns -2ns | Input or I/O pair
7 8 0V 1ns NA NA | Output* pin pair
9 10 NA NA NA NA | Output* pin pair
16 15 200mV 1ns | Input or I/O pin pair
20 19 0V NA | Output* pin pair, tdelay = 0ns
22 21 NA NA | Output*, tdelay = 0ns
| * Could be Input or I/O with vdiff = 0V
******************************************************************************
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION
Since only a small percentage of components contain differential pins,
[Diff_Pin] is optional. The component itself may be required to convey the
associations between pins for differential inputs and/or outputs. Such cases
may occur in practice when pairs of pins are connected using closely-spaced,
coupled nets or twisted-pair cabling.
Pins which provide complimentary outputs should not be associated with
each other when the analysis is normally done using only one pin at a
time. However, there may be cases related to other pending extensions
(package models, power association, etc.) where association of complimentary
pins may be appropriate.
[Diff_pin] should be used for pins designed for differential operation.
Inputs of such components have differential input sensitivity specifications
such as "Vpp" or "VT+" and "VT-" which define the differential threshold
voltages between two input pins. The vdiff column is introduced for such
specification limits (the magnitudes used for both polarities) which would
trigger an output change. Two switching cycles show that the actual switching
can occur at either polarity vdiff relative to one pin (A0_bar). If the actual
switching completes near tmax (the threshold past the cross-over), then the
first switching completes when (A0 - A0_bar) is negative and the second when
(A0 - A0_bar) is positive. One application of vdiff is for timing analysis
bounds.
|<-- OUTPUT MEASUREMENT POINT FROM ANOTHER COMPONENT
| __
| Polarities of vdiff relative to A0 signal show both
|<-- tmax -->| polarities used to bound the transition region
| |
|<-- tmin ->|| (output = 0) (output = 1)
__________ || ____________ _____________
\ || / \ / A0
__\||/__ __\ /__
+ \/ - vdiff - \/ + DIFFERENTIAL INPUT
__ /\ __ __ /\ __
/ \ / \ __
__________/ \____________/ \_____________ A0
For timing purposes, an output is referenced to an equal voltage cross-over
of output pins. Setting the vdiff entry to 0V is thus chosen when the pins
are for differential outputs only. Note, the cross-over does NOT mean that
the outputs are at 0V.
The Tskew value is the time difference between the mid-point of the two
output transitions. It is equivalent to the time-delay of one pin relative
to the other pin. Although an absolute value is specified, either pin can
delayed relative to the other pin. This specification assumes the outputs
are reasonably identical and the rise and fall transitions are reasonably
similar. tdelay may relate to Tskew values of unloaded outputs, but
are considered separate in IBIS as a launch delay of the non-inverting
output relative to the inverting output. tdelay can be either polarity.
Tskew can be shown per National Interface Databook, diagram on pg 1-121
along with tdelay:
3V _______________
/ \ INPUT TO SAME COMPONENT
1.5V__ / \
/| |\
0V ___/ | | \______________
| tPLH | |tPHL|
___________ __________ _________ __
^ ^ |\ Tskew/ \ / ^ D0
| Vo/2 | \|<>|/ \/ Vo/2
Vo v__ | _\ /__ __|/\|_____v DIFFERENTIAL OUTPUT
| \/ / \
| | /\ /| |\
v_________|__/ \__________/ | | \_______ D0
| | | |
| | >| |< Tskew Tskew = |tPLH - tPHL|
| |
>| |< tdelay (positive value)
Conventions similar to those in [Pin] are followed with respect to required
and optional column entries and to column lengths.
******************************************************************************
ANY OTHER BACKGROUND INFORMATION:
Introducing a [Tskew] keyword similar to [Package] (used for defaults) was
suggested and could be considered as another method for dealing with skew.
(This would not apply for tdelay due to polarity convention.)
An alternative polarity mechanism for differential outputs could have been
based on the Polarity sub-parameter within the [Model]. This was not done
because Polarity is optional and also because two [Model]s would be
required: one for the "Non-inverting" pin and another for the "Inverting"
pin. In BIRD6.1, vdiff is used as an absolute difference regardless of
polarity for Input specfication, so "polarity" no longer is applicable for
inputs.
However, it still may be reasonable to require two Output or I/O [Model]s
for easier translation into simulator databases. In this case, the "inv_pin"
name could be changed to "2nd_pin". Also, with a Polarity sub-parameter,
the possibility exists that the [Models] are in phase with each other. This
may be useful for double strength buffer options.
*** BIRD6.0 to BIRD6.1 Changes ***
vpp renamed to vdiff, and polarity specification modified.
tskew_typ, tskew_max, tskew_min columns added.
Note regarding vinl and vinh removed since it was not relevant.
Analysis Path text revised and expanded.
Note on vdiff notation:
Motorola uses Vpp in ECLinPS family
TI uses VT+ and VT- in Data Transmission Circuits Family
National uses VTH in Interface Databook
*** BIRD6.1 to BIRD6.2 Changes ***
On "vdiff", clarification and definition changes:
As Syed Hug pointed out this parameter can be used as a (maximum)
differential voltage threshold limit between two inputs, and
to respond to Jon Powell's polarity question he gave an example
of how this limit would be one polarity for the first transition,
and the opposite polarity for the second transition (relative to
one of the pins). Since neither Jon nor I have seen any example
where the VT+ and VT- limits are of different magnitudes, the
"vdiff" is specified by one value. I have taken the liberty
to redefine the parameter in the text as "differential threshold
voltage" to emphasize that it is a threshold limit voltage
specification rather than an actual voltage. The diagram in the
Analysis Path shows two cycles and the polarities of "vdiff".
On "tskew", name and context change to "tdelay":
My attempt to correlate "tskew" with anything published failed based
on the comments from Bob Canright, Will Hobbs and Kellee Crisafulli.
In fact data book "tskew" numbers would not be relevant for technical
reasons including load, incomplete partioning of other parameters such
as output capacitance, etc. The original intent of the parameter was to
capture the "launch" time differences between the non-inverting and
inverting outputs of differential pins. The term has been changed to
"tdelay" to mean the delay of the non-inverting transition relative to the
inverting transition. The delay can be + or -. If it is "+", then
the non-inverting transition is launched at "tdelay" after the inverting
transition starts. If the delay is "-", then the inverting transition
is launched at |tdelay| after the non-inverting transition starts. The
description and diagram have been modified to show this.
Based on comments from Stephen Peters, the tdelay specification has to
be one provided by the manufacturer. It could relate to internal
transistor delays, packaging delays, etc. Thus, if the manufacturer
provides a full package description showing different L_pin values,
the tdelay entries might be 0ns. Alternatively, the tdelay entries
may account for variations when only L_pkg is used. The manufacturer
can provide entries of tdelay based on other known internal variations
or variation limits.
No action is taken regarding the parameters brought up by Stephen and
Syed such as differential propagation delay and output-to-output skew.
It is not clear that such information should fall within IBIS.
******************************************************************************
Received on Sun Feb 6 02:26:10 1994
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