To IBIS committee and Steve
Steve, your Spice to IBIS work and progress is very impressive. I now have
several brief comments based on a quick review and an IBIS_CHK of your results.
(1) Version 1.1 of IBIS requires that C_comp be defined for all models,
and this shows up as an error in your example. After this is corrected,
and a [RAMP] is inserted, your IBIS results pass IBIS_CHK.
(2) In the DESCRIPTION section for the manual, you indicate that Open_drain
omits the [POWER_clamp] table. This table can exist and should be inserted,
if it exists, into Open_drain models.
(3) In the INPUT FILE section, there needs to be a method to enter "vih"
and "vil" for I/O models as well as Input. As a result of a Version 1.1
potential "oversite", This information is not checked by IBIS_CHK. In
practice, it is a virtual requirement for timing analysis. Based on the
writeup, it appears to be impossible to enter this information for I/O pins.
Also, I notice that the Input models in your example do not contain the
Vinh and Vinl information.
Thank you for posting the results so quickly. Great Job!!!
Bob Ross, Interconnectix, Inc.
Received on Fri Mar 11 17:47:47 1994
This archive was generated by hypermail 2.1.8 : Fri Jun 03 2011 - 09:52:28 PDT