comments on the diet 0.9 format ref manual

I received the following comments on the DIET Format from Peter Ting of
Teradyne. In the interest of stimulating some discussion I am distributing
them to the dietech reflector. Please take a few minutes to review them and
send your comments back to me at dietech@vhdl.org. Also, don't hesitate to
forward this to anyone you think might be interested. I can use all the
feedback I can get.

Thanks due to Peter for taking the time to put together the comments.
Peter's comments are at least partially the result of his writing a DIET
model of a 74act646 component. If you would like me to email you a copy of his
model, please contact me. I will seek Peter's permission to send you a
copy.
 
>Date: Mon, 28 Nov 94 12:19:51 EST
>From: ting.peter@atb.teradyne.com (Peter Ting)
>Message-Id: <9411281719.AA24852@bamboo.ATB.Teradyne.COM>
>Received: by flame.beekeeper (4.1/SMI-4.1)
> id AA11747; Mon, 28 Nov 94 12:20:42 EST
>To: lfs@synopsys.com
>Subject: comments on the diet 0.9 format ref manual
>Content-Length: 2199
>X-UIDL: 786046744.019
>
>Hi Larry
>
>Have the following comments regarding the DIET 0.9 Format Ref Manual
>
>1-on pg 7, Output Hold Time is actualy minimal delay time. ie the
> outputs will NOT change befor the hold time.
>
>2-There should be a notes section in the ACTUAL_COMPONENT section
> for multi vender diet stuff.
>
>3-We should allow nc -no connect, and vcc,gnd etc pins in the
> PACKAGE setting
>
>4-on pg 42, Why is the hold_time_spec order different from the
> setup_time_spec, ie data ->clock.
>
>5-on pg 42, <time_spec_name> should include CHANGE, ie both rising/falling
>
>6-on pg 42, <to_edge> should include ANY, ie both rising/falling
>
>7-on pg 51, <transitions> v_m0 and v_m1 should be v_mo and v_mi
> ie Voltage_measurement_output and voltage_measurement_input
> The order should also be reversed to input first, then output.
>
>8-on pg 51, the Capacitive values must be defined in units of FARADS???
> Can we change this default? Seems to be a easy mistake to make.
>
>9-We are missing some common test conditions, ie Tr (rise time) and
> Tf (fall time). There is a second order (analog) effect between rise time
> and propgation delay time. This is important!
>
>10-We are missing Vin for Logic low and Vin for logic high for test conditions.
>
>11-An additional use of the data_stream construct could be the timing diagrams.
> These could provide a pictioral information on how the timing data should
> be interperted.
>
>12-General comment. There seems to be redudency in the diet format with
> respect to operating_condition and test_condition. ie both specify the
> ambient tempeture range, and voltage range. Infact, the operating
> condition setting seems to be a subset of the test_condition setting.
> This duplication of data might be OK since the data book duplicates
> the data also.
>
>
>PS. There is a product called TimingDesigner from Chronology that seems to
> address some of the timing issues. In particualar, there is an
> interactive databook from intel. Chronology's email address is
> chronco!sales@uunet.uu.net. Phone 1-800-800-6494. Am getting a
> free evaluation kit to check it out. If we could get them to output
> data in DIET format??
>
>
>P.Ting
>
>

Larry Saunders
lfs@mcimail.com or lfs@synopsys.com
408-894-0119 415-694-1837
408-894-0119 (fax) 415-965-8637 (fax)
1426 Cedarmeadow Ct 700 East Middlefield Rd, Bldg C
San Jose, CA Mountain View, CA
95131 94043-4033
Received on Mon Nov 28 11:48:04 1994