Commnets on IBIS FAQ

Thanks to Syed for putting together the IBIS FAQ. When I first started looking
into IBIS, such a thing would have definitely been very useful to me. I had a
few suggestions on the FAQ. Here they are:

1. Item 1 mentions that IBIS "can be used to model almost 99% of all
   semiconductor". I think we could just make it "most semiconductors".

2. Item 6 regarding SSO could mention the advantages of using Ver 2.1 models
   over Ver 1.1. The use of a matrix for the inductance accounts for the "loop"
   inductance i.e. the mutuals between the pins are considered. Usually
   the mutuals help in reducing the net inductance. Moreover, Ver 2.1 contains
   information on which driver/receiver is connected to which GND/VCC pin.
   This information is vital for SSO simulations.

   Most of the models in the IBIS library are Version 1.1 models and users
   must understand the limitations of these models from a SSO viewpoint.

3. The need to sweep from -VCC to 2VCC is not related to SPICE convergence.
   SPICE will have no problems converging with 0 to VCC sweep models. The main
   reason is that reflections caused by improper terminations can produce
   voltages at the driver/receiver terminals from -VCC to 2VCC. The drivers
   and receivers, therefore, need to be modeled over this entire range.

4. Some clarifications on the use and origin of C_comp would be very helpful.

5. There is considerable confusion on the use of IBIS models versus SPICE. Some
   clarifications and comparison would be useful. It is not a IBIS vs SPICE
   issue as much as a IBIS versus transistor model issue. Many SPICE vendors
   themselves directly take in IBIS models and can simulate them along with
   other SPICE elements. Where transistor models are available,it may still be
   best to use them.

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Raj Raghuram
Contec CAE,
2188 Bering Drive,
San Jose, CA-95131.
Tel: (408) 434-6767 ext.131
Fax: (408) 434-6884
e-mail: raghu@contec.com
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Received on Mon Aug 7 15:51:08 1995